EP1SGX40DF1020C7N Altera, EP1SGX40DF1020C7N Datasheet - Page 55
EP1SGX40DF1020C7N
Manufacturer Part Number
EP1SGX40DF1020C7N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Figure 3–5. Source-Synchronous DPA Circuitry
Note to
(1)
Altera Corporation
August 2005
Both deserializers are identical. The deserializer operation is described in the
section.
Figure
rx_inclock_p
rx_inclock_n
3–5:
rx_in+
rx_in-
Receiver Circuit
DPA Block Overview
Each Stratix GX receiver channel features a DPA block. The block contains
a dynamic phase selector for phase detection and selection, a SERDES, a
synchronizer, and a data realigner circuit. You can bypass the dynamic
phase aligner without affecting the basic source-synchronous operation
of the channel by using a separate deserializer shown in
The dynamic phase aligner uses both the source clock and the serial data.
The dynamic phase aligner automatically and continuously tracks
fluctuations caused by system variations and self-adjusts to eliminate the
phase skew between the multiplied clock and the serial data.
shows the relationship between Stratix GX source-synchronous circuitry
and the Stratix GX source-synchronous circuitry with DPA.
PLL
×W
8
×1
Dynamic
Aligner
Phase
Deserializer
Deserializer (1)
(1)
Source-Synchronous Signaling With DPA
Stratix GX Device Handbook, Volume 1
“Principles of SERDES Operation”
Stratix GX
Logic
Array
Figure
Figure 3–5
3–5.
3–5
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