EP1SGX40DF1020C7N Altera, EP1SGX40DF1020C7N Datasheet - Page 67
EP1SGX40DF1020C7N
Manufacturer Part Number
EP1SGX40DF1020C7N
Description
IC STRATIX GX FPGA 40K 1020-FBGA
Manufacturer
Altera
Series
Stratix® GXr
Datasheet
1.EP1SGX10CF672C7N.pdf
(272 pages)
Specifications of EP1SGX40DF1020C7N
Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
624
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Logic Array
Blocks
Figure 4–1. Stratix GX LAB Structure
Altera Corporation
February 2005
SGX51004-1.0
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Local Interconnect
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, local
interconnect, LUT chain, and register chain connection lines. The local
interconnect transfers signals between LEs in the same LAB. LUT chain
connections transfer the output of one LE’s LUT to the adjacent LE for fast
sequential LUT connections within the same LAB. Register chain
connections transfer the output of one LE’s register to the adjacent LE’s
register within an LAB. The Quartus
within an LAB or adjacent LABs, allowing the use of local, LUT chain,
and register chain connections for performance and area efficiency.
Figure 4–1
LAB Interconnects
The LAB local interconnect can drive LEs within the same LAB. The LAB
local interconnect is driven by column and row interconnects and LE
outputs within the same LAB. Neighboring LABs, M512 RAM blocks,
LAB
shows the Stratix
4. Stratix GX Architecture
Three-Sided Architecture—Local
Interconnect is Driven from Either Side by
Columns & LABs, & from Above by Rows
®
GX LAB.
Row Interconnects of
Variable Speed & Length
®
II Compiler places associated logic
Column Interconnects of
Variable Speed & Length
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
4–1
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