EP1S40F1020C5 Altera, EP1S40F1020C5 Datasheet - Page 145

• Manufacturer Part Number: EP1S40F1020C5
• Description: IC STRATIX FPGA 40K LE 1020-FBGA
• Manufacturer: Altera
• Series: Stratix®r

Specifications of EP1S40F1020C5

• Number Of Logic Elements/cells: 41250
• Number Of Labs/clbs: 4125
• Total Ram Bits: 3423744
• Number Of I /o: 773
• Voltage - Supply: 1.425 V ~ 1.575 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1020-FBGA
• Family Name: Stratix
• Number Of Logic Blocks/elements: 41250
• # I/os (max): 773
• Frequency (max): 500MHz
• Process Technology: 0.13um (CMOS)
• Operating Supply Voltage (typ): 1.5V
• Logic Cells: 41250
• Ram Bits: 3423744
• Operating Supply Voltage (min): 1.425V
• Operating Supply Voltage (max): 1.575V
• Operating Temp Range: 0C to 85C
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 1020
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Not Compliant
• Other names: 544-2089

Altera Corporation
July 2005
EP1S10
EP1S20
Table 2–37. EP1S10, EP1S20 & EP1S25 Device Differential Channels (Part 1 of 2)
Device
484-pin FineLine BGA Transmitter
672-pin FineLine BGA
672-pin BGA
780-pin FineLine BGA Transmitter
484-pin FineLine BGA Transmitter
672-pin FineLine BGA
672-pin BGA
780-pin FineLine BGA Transmitter
Package
Table 2–37
EP1S10, EP1S20, and EP1S25 devices.
show this information for EP1S30, EP1S40, EP1S60, and EP1S80 devices.
Receiver
Transmitter
Receiver
Receiver
Receiver
Transmitter
Receiver
Receiver
Transmitter/
Receiver
shows the number of channels that each fast PLL can clock in
(2)
(2)
(2)
(2)
(2)
(2)
Channels
Total
20
20
36
36
44
44
24
20
48
50
66
66
Maximum
840
840
840
840
624
624
624
624
840
840
840
840
840
840
840
840
624
624
624
624
840
840
840
840
(Mbps)
Speed
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
(4)
(3)
Tables 2–38
Stratix Device Handbook, Volume 1
PLL 1
10
10
18
18
11
22
11
22
12
10
12
24
13
25
17
33
17
33
5
5
9
9
6
5
Center Fast PLLs
PLL 2
through
Note (1)
10
10
18
18
11
22
11
22
12
10
12
24
12
25
16
33
16
33
5
5
9
9
6
5
Stratix Architecture
PLL 3
Table 2–41
10
10
18
18
11
22
11
22
12
10
12
24
12
25
16
33
16
33
5
5
9
9
6
5
PLL 4
2–131
10
10
18
18
11
22
11
22
12
10
12
24
13
25
17
33
17
33
5
5
9
9
6
5