EP1S40F1020C5 Altera, EP1S40F1020C5 Datasheet - Page 262

no-image

EP1S40F1020C5

Manufacturer Part Number
EP1S40F1020C5
Description
IC STRATIX FPGA 40K LE 1020-FBGA
Manufacturer
Altera
Series
Stratix®r
Datasheet

Specifications of EP1S40F1020C5

Number Of Logic Elements/cells
41250
Number Of Labs/clbs
4125
Total Ram Bits
3423744
Number Of I /o
773
Voltage - Supply
1.425 V ~ 1.575 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1020-FBGA
Family Name
Stratix
Number Of Logic Blocks/elements
41250
# I/os (max)
773
Frequency (max)
500MHz
Process Technology
0.13um (CMOS)
Operating Supply Voltage (typ)
1.5V
Logic Cells
41250
Ram Bits
3423744
Operating Supply Voltage (min)
1.425V
Operating Supply Voltage (max)
1.575V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1020
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Not Compliant
Other names
544-2089

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
Quantity:
5 510
Part Number:
EP1S40F1020C5
Manufacturer:
XILINK
Quantity:
5 510
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA30
Quantity:
113
Part Number:
EP1S40F1020C5
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
Quantity:
6 000
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
Quantity:
6 000
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA
0
Part Number:
EP1S40F1020C5
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Part Number:
EP1S40F1020C5
0
Part Number:
EP1S40F1020C5ES
Manufacturer:
ALTERA
0
Part Number:
EP1S40F1020C5N
Manufacturer:
ALTERA
Quantity:
3 000
Part Number:
EP1S40F1020C5N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
f
frequency)
(LVDS,LVPECL,
HyperTransport
technology)
f
f
(LVDS,LVPECL,
HyperTransport
technology)
f
frequency)
(PCML)
f
Device operation,
f
(PCML)
TCCS
HSCLK
HSCLK
HSDR
H S C L K
HSCLK
H S D R
Table 4–126. High-Speed I/O Specifications for Wire-Bond Packages (Part 1 of 2)
Device operation,
(Clock
= f
= f
(Clock
Symbol
HSDR
HSDR
/ W
/ W
W = 4 to 30 (Serdes used)
W = 2 (Serdes bypass)
W = 2 (Serdes used)
W = 1 (Serdes bypass)
W = 1 (Serdes used)
J = 10
J = 8
J = 7
J = 4
J = 2
J = 1 (LVDS and LVPECL
only)
W = 4 to 30 (Serdes used)
W = 2 (Serdes bypass)
W = 2 (Serdes used)
W = 1 (Serdes bypass)
W = 1 (Serdes used)
J = 10
J = 8
J = 7
J = 4
J = 2
J = 1
All
Conditions
Min
150
100
300
300
300
300
300
100
100
150
100
300
300
300
300
300
100
100
10
50
10
50
-6 Speed Grade
Typ
77.75
155.5
Max
156
231
312
311
624
624
624
624
624
462
311
150
200
311
311
311
311
311
300
200
400
Min
150
100
300
300
300
300
300
100
100
100
100
100
10
50
50
-7 Speed Grade
Typ
115.5
Max
77.5
231
231
270
462
462
462
462
462
462
270
155
155
155
400
Min
150
100
300
300
300
300
300
100
100
100
100
100
10
50
50
-8 Speed Grade
Typ
115.5
Max
77.5
231
231
270
462
462
462
462
462
462
270
155
155
155
400
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
Unit
ps

Related parts for EP1S40F1020C5