EP2SGX90EF1152C3N Altera, EP2SGX90EF1152C3N Datasheet - Page 238

IC STRATIX II GX 90K 1152-FBGA

EP2SGX90EF1152C3N

Manufacturer Part Number
EP2SGX90EF1152C3N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet

Specifications of EP2SGX90EF1152C3N

Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1766
EP2SGX90EF35C3NES

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90EF1152C3N
Manufacturer:
Altera
Quantity:
10 000
Part Number:
EP2SGX90EF1152C3N
Manufacturer:
ALTERA
0
Part Number:
EP2SGX90EF1152C3N
Manufacturer:
ALTERA
Quantity:
100
Part Number:
EP2SGX90EF1152C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
Timing Model
4–68
Stratix II GX Device Handbook, Volume 1
Notes to
(1)
(2)
(3)
(4)
(5)
(6)
(7)
TriMatrix
Memory
MegaRAM
block
(cont.)
block
DSP
Table 4–55. Stratix II GX Performance Notes (Part 3 of 3)
These design performance numbers were obtained using the Quartus II software.
This column refers to -3 speed grades for EP2SGX30, EP2SGX60, and EP2SGX90 devices.
This column refers to -3 speed grades for EP2SGX130 devices.
This application uses registered inputs and outputs.
This application uses registered multiplier input and output stages within the DSP block.
This application uses registered multiplier input, pipeline, and output stages within the DSP block.
This application uses registered multiplier inputs with outputs of the multiplier stage feeding the accumulator or
subtractor within the DSP block.
Applications
Table
Single port RAM
64K x 9 bit
dual-port RAM
64K x 9 bit
RAM 64K x 9 bit
9 x 9-bit
multiplier
18 x 18-bit
multiplier
18 x 18-bit
multiplier
36 x 36-bit
multiplier
36 x 36-bit
multiplier
18-bit, 4-tap FIR
filter
Simple
True dual-port
4–55:
(5)
(5)
(7)
(5)
(6)
ALUTs
0
0
0
0
0
0
0
0
0
Resources Used
TriMatrix
Memory
Blocks
1
1
1
0
0
0
0
0
0
Blocks
DSP
0
0
0
1
1
1
1
1
1
-3 Speed
Grade
364.96
420.16
359.71
430.29
410.17
450.04
410.17
410.17
250.0
Note (1)
(2)
Speed
Grade
347.22
342.46
409.16
390.01
428.08
238.15
390.01
390.01
400.0
(3)
-3
Performance
-4 Speed
Grade
325.73
375.93
322.58
403.22
224.01
385.2
367.1
367.1
367.1
Altera Corporation
271.73
313.47
268.09
305.06
335.12
305.06
305.06
Speed
Grade
320.1
186.6
-5
June 2009
Units
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz
MHz

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