EP2SGX90EF1152C3N Altera, EP2SGX90EF1152C3N Datasheet - Page 287
EP2SGX90EF1152C3N
Manufacturer Part Number
EP2SGX90EF1152C3N
Description
IC STRATIX II GX 90K 1152-FBGA
Manufacturer
Altera
Series
Stratix® II GXr
Datasheet
1.EP2SGX90EF1152C3N.pdf
(316 pages)
Specifications of EP2SGX90EF1152C3N
Number Of Logic Elements/cells
90960
Number Of Labs/clbs
4548
Total Ram Bits
4520448
Number Of I /o
558
Voltage - Supply
1.15 V ~ 1.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
1152-FBGA
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
816.9MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
0C to 85C
Operating Temperature Classification
Commercial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
For Use With
544-1725 - PCIE KIT W/S II GX EP2SGX90N544-1724 - SI KIT W/SII GX EP2SGX90N544-1702 - VIDEO KIT W/SII GX EP2SGX90N
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Other names
544-1766
EP2SGX90EF35C3NES
EP2SGX90EF35C3NES
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
EP2SGX90EF1152C3N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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(1)
(2)
(3)
(4)
1.5-V differential
HSTL Class II
3.3-V PCI
3.3-V PCI-X
LVDS
LVPECL
3.3-V LVTTL
2.5-V LVTTL
1.8-V LVTTL
3.3-V LVCMOS
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.2-V HSTL
Table 4–97. Maximum Output Clock Toggle Rate Derating Factors (Part 5 of 5)
I/O Standard
For LVDS output on row I/O pins the toggle rate derating factors apply to loads larger than 5 pF. In the derating
1.2-V HSTL is only supported on column I/O pins on -3 devices.
LVPECL is only supported on column clock outputs.
calculation, subtract 5 pF from the intended load value in pF for the correct result. For a load less than or equal to
5 pF, refer to
Differential HSTL and SSTL is only supported on column clock and DQS outputs.
(4)
(2)
(3)
Tables 4–91
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
OCT 25 Ω
OCT 50 Ω
Strength
16 mA
18 mA
20 mA
Drive
through
134
134
133
207
151
300
157
121
100
95
95
94
56
61
95
-3
4–95
-
-
Column I/O Pins
Maximum Output Clock Toggle Rate Derating Factors (ps/pF)
for output toggle rates.
101
100
101
177
177
152
274
165
316
171
134
101
123
110
-4
-
-
-
101
100
101
177
177
152
274
165
316
171
134
101
123
110
-5
-
-
-
155
133
207
151
300
157
121
100
56
-3
-
-
-
-
-
-
-
-
(1)
Row I/O Pins
155
152
274
165
316
171
134
101
123
(1)
-4
-
-
-
-
-
-
-
-
155
152
274
165
316
171
134
101
123
(1)
-5
-
-
-
-
-
-
-
-
101
104
143
143
134
134
147
235
153
263
174
106
96
77
58
59
95
-3
Dedicated Clock
Outputs
101
100
101
177
177
134
134
152
274
165
316
171
134
101
123
110
-4
-
101
100
101
177
177
134
134
152
274
165
316
171
134
101
123
110
-5
-
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