EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet

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EP4SE530H35C2N

Manufacturer Part Number
EP4SE530H35C2N
Description
IC STRATIX IV FPGA 530K 1152HBGA
Manufacturer
Altera
Series
STRATIX® IV Er

Specifications of EP4SE530H35C2N

Number Of Logic Elements/cells
531200
Number Of Labs/clbs
21248
Total Ram Bits
27376
Number Of I /o
744
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
1152-HBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

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EP4SE530H35C2NES
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ES-01024-2.5
Production Device Issues for Stratix IV E Devices
Table 1. Production Device Issues for Stratix IV E Devices
March 2011 Altera Corporation
101 Innovation Drive
San Jose, CA 95134
www.altera.com
“I/O Jitter”
Affected Stratix IV E production devices may exhibit higher than
expected jitter on general purpose I/O pins.
“Fast Passive Parallel (FPP) Mode Configuration Failures at High
DCLK Frequency”
Stratix IV E configuration might fail in FPP mode when the DCLK
frequency is set to 125 MHz with a 60/40 or 40/60 duty cycle.
“FPP Mode Configuration Failures When the Minimum Hold Time
(t
Stratix IV E configuration fails in FPP mode when the minimum
data hold time (t
unencrypted configuration data or 24 ns for compressed and/or
encrypted data.
“M144K RAM Block Lock-Up”
M144K RAM blocks may lock up if there is a glitch in the clock
source.
“Stratix IV E Power-up Sequencing on Production Devices”
The device fails to power up and exit POR at low temperatures
when V
“Higher Power Supply Current During Power-Up for V
Higher power-up current requirements are needed for V
power supply.
DH
) is set to 0 ns or 24 ns”
CC
is powered after V
DH
) is set to 0 ns for uncompressed and
www.altera.com/common/legal.html. Altera warrants performance of its semiconductor products to current specifications in
accordance with Altera’s standard warranty, but reserves the right to make changes to any products and services at any time
without notice. Altera assumes no responsibility or liability arising out of the application or use of any information, product, or
service described herein except as expressly agreed to in writing by Altera. Altera customers are advised to obtain the latest
version of device specifications before relying on any published information and before placing orders for products or services.
© 2011 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS,
QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries.
All other trademarks and service marks are the property of their respective holders as described at
This errata sheet provides updated information about known device issues affecting
Stratix
Table 1
CCAUX
Issue
®
lists the specific issues and the affected Stratix IV E production devices.
IV E devices.
.
CCPD
CCPD
Errata Sheet for Stratix IV E Devices
EP4SE360, EP4SE530,
All production devices
All production devices
All production devices
All production devices
All production devices
Affected Devices
EP4SE820
Refer to
Supply Current During
Power-Up for V
EP4SE360 Rev B,
EP4SE530 Rev E,
EP4SE820 Rev B
Planned Fix
“Higher Power
CCPD
Errata Sheet
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EP4SE530H35C2N Summary of contents

Page 1

... Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX are Reg. U.S. Pat. & Tm. Off. and/or trademarks of Altera Corporation in the U.S. and other countries. All other trademarks and service marks are the property of their respective holders as described at www ...

Page 2

... The actual amount of additional jitter depends on the device switching activity. The EP4SE230 production ordering code is not affected. Altera is fixing this issue in the next revision of production devices, which will meet all current jitter specifications. f For further support, file a service request using mysupport.altera.com. ...

Page 3

... Assignment Editor. The global and per instance assignments can be mixed. For example, you can set DCD to On globally, but set it to Off for an instance. You can also only set instance. March 2011 Altera Corporation ® II software version 9.1 to work around this performance is ...

Page 4

... CCAUX 1 You can successfully use the hot socketing feature if you use the V power sequence board design modification. Contact Altera for Technical Support if you require assistance with implementing these board design changes. Stratix Device Issues Table 2 shows the specific issues and which Stratix devices are affected by each issue ...

Page 5

... Quartus II software version 9.0 SP2. March 2011 Altera Corporation Affected Devices EP4SE530 ES EP4SE530 ES EP4SE530 ES EP4SE530 ES supply. CC EP4SE530 ES EP4SE530 ES ® II software version 9.1, or contact Altera Page 5 Planned Fix Production devices devices Production devices devices EP4SE530 devices production devices EP4SE530 devices production devices ...

Page 6

... This issue only occurs with the error injection block and is fixed in production devices. The CRC Error Detection feature operates correctly as expected, and is not affected by this issue. If you need to use the CRC Error Injection feature with ES devices, contact Altera Technical Support. Higher Power Supply Current During Power-Up for V Stratix devices require higher power-up current levels for the V supply than previously specified ...

Page 7

... Quartus II software will prevent this issue from occurring in ES devices. This issue is fixed in production devices. f You can download a software patch to help with the CRC Error Detection feature issue at: http://www.altera.com/support/kdb/solutions/rd04092009_699.html March 2011 Altera Corporation Page 7 Errata Sheet for Stratix IV E Devices ...

Page 8

... Stratix devices may exhibit ± ~100 ps higher than expected jitter on all I/O pins. The actual amount of additional jitter is application and toggle-rate dependent. Altera fixed the issue in production devices, which meets all current jitter specifications. If you are using ES devices, you need to account for this additional timing uncertainty in all I/O timing closure budgets ...

Page 9

... LVDS receivers configured in Soft CDR mode with 0 PPM difference (synchronous interface) are also affected. For applications with flexibility in the choice of training patterns, Altera recommends you choose bit sequences with more data transitions and a non-cyclical pattern similar to a PRBS or K28.5 code sequence. ...

Page 10

... For more information about the DPA PLL Calibration feature, refer to the Transmitter/Receiver (ALTLVDS) Megafunction User Guide corresponding to the Quartus II software version 9.0. Until the User Guide is updated, in the interim, contact the Altera mySupport page at www.mysupport.altera.com. Document Revision History Table 5 lists the revision history for this Errata Sheet. ...

Page 11

Table 5. Document Revision History (Part Date Version August 2009 1.1 June 2009 1.0 Added “Remote System Upgrade” M9K/M144K RAM Block Lock-up ■ CRC Error Injection Feature ■ Higher Power Supply Current During Power-Up for V ■ ...

Page 12

... Page 12 Errata Sheet for Stratix IV E Devices Document Revision History March 2011 Altera Corporation ...

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