EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 10

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Page 10
Document Revision History
Table 5. Document Revision History (Part 1 of 2)
Errata Sheet for Stratix IV E Devices
March 2011
January 2011
May 2010
April 2010
January 2010
November 2009
Date
f
1
There are two caveats when enabling the DPA PLL Calibration feature:
■
■
For more information about the DPA PLL Calibration feature, refer to the
Transmitter/Receiver (ALTLVDS) Megafunction User Guide
corresponding to the Quartus II software version 9.0. Until the User Guide is updated,
in the interim, contact the Altera mySupport page at www.mysupport.altera.com.
Table 5
Version
PLL merging (merging RX and RX or merging RX and TX PLL) is not
automatically supported by the ALTLVDS megafunction; use the external PLL
option to handle PLL merging separately.
Timing for all PLL outputs is pulled in by 1/4 of the voltage controlled oscillator
(V
for external I/O pin timing interfaces and for clock domain transfers (without a
FIFO) when the clocks are not all from this same PLL.
2.5
2.4
2.3
2.2
2.1
2.0
CO
lists the revision history for this Errata Sheet.
) phase during the PLL calibration process. This must be taken into account
Update the “I/O Jitter” section of
■
■
■
■
■
■
■
■
■
Added:
■
■
■
Updated the following with link to software patch:
■
■
Updated with fix in “Automatic Clock Switchover”.
Updated the “Fast Passive Parallel (FPP) Mode Configuration Failures at High
DCLK Frequency” section.
Converted to the new template.
Added the “I/O Jitter” section.
Added “Fast Passive Parallel (FPP) Mode Configuration Failures at High DCLK
Frequency”
Added “FPP Mode Configuration Failures When the Minimum Hold Time (tDH) is
set to 0 ns or 24 ns”
Updated “DPA Misalignment” and removed this issue from Production devices
section
Updated “Higher Power Supply Current During Power-Up for VCCPD”
Updated “Stratix IV E Power-up Sequencing on Production Devices”.
Added “DPA Misalignment” section to production devices.
“Stratix IV E Production Device Issues”
“M144K RAM Block Lock-Up”
“Stratix IV E Power-up Issue on Production Devices”
“M144K Write with Dual-Port Dual-Clock Modes”
“CRC Error Detection Feature”
Table
Changes
1.
planned release
March 2011 Altera Corporation
Document Revision History
SERDES