EP4SE530H35C2N Altera, EP4SE530H35C2N Datasheet - Page 6

• Manufacturer Part Number: EP4SE530H35C2N
• Description: IC STRATIX IV FPGA 530K 1152HBGA
• Manufacturer: Altera
• Series: STRATIX® IV Er

Specifications of EP4SE530H35C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1152-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Page 6
Errata Sheet for Stratix IV E Devices
M9K/M144K RAM Block Lock-up
CRC Error Injection Feature
Higher Power Supply Current During Power-Up for V
The M9K and M144K blocks can lock up if the clock source glitches when rden=1,
which can occur if the clock source is not from a PLL. In this state, a RAM block no
longer responds to read or write operations and requires an FPGA reconfiguration to
restore operation. The issue occurs in the Read Timer Trigger circuitry, where a
glitch-prone non-PLL clock may inadvertently freeze the Read Timer Trigger circuitry,
locking the RAM block in its last operation. All RAM block modes are affected.
MLABs are not affected.
The workaround is to add clock-enable logic, an internal PLL, or clock generation
logic (for example, a clock divider). You can add clock-enable logic (internal or
external) to disable RAM block operation until the clock is stable. You can also gate
the clock internally or externally. If FPGA resources permit, you can use an internal
PLL or clock generation logic to ensure a stable clock source at the RAM block input.
The CRC Error Injection feature on Stratix IV E ES devices may not operate correctly
when running the EDERROR_INJECT JTAG instruction. The CRC_ERROR output status pin
may remain low, incorrectly indicating no CRC errors.
This issue only occurs with the error injection block and is fixed in production
devices. The CRC Error Detection feature operates correctly as expected, and is not
affected by this issue.
If you need to use the CRC Error Injection feature with ES devices, contact Altera
Technical Support.
Stratix IV E ES devices require higher power-up current levels for the V
supply than previously specified. The PowerPlay Early Power Estimator (EPE)
version 9.0.1 correctly shows the V
Quartus II software and PowerPlay EPE version 9.1 and later versions correctly show
the V
Stratix IV E ES and production device functionality is not affected by this issue, even if
your V
Quartus II software and/or EPE specify. Stratix IV E ES and production devices will
power-up and operate correctly as expected, provided the supplies power up
monotonically and the minimum voltage requirement is met. V
minimum power supply voltage requirement for the device to exit power-on reset
(POR). After the device exits POR, the V
reported by Altera’s power estimation tools. Overall thermal power and operating
current levels are not affected by this issue.
If there are other devices on the board that share the V
use the Quartus II software and/or the EPE to estimate power supply current
requirements. This analysis may be needed if the other devices on the board have
stringent power supply integrity requirements.
There is no planned fix for the higher power-up current requirements.
CCPD
CCPD
power-on current for production devices.
power supply is designed with output current levels below what the
CCPD
CCPD
power-on current for ES devices. The
current requirements return to what is
CCPD
CCPD
power supply, you can
March 2011 Altera Corporation
CCPD
Stratix IV E ES Device Issues
must meet the
CCPD
power
®