EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 28

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

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Document Revision History
Table 9. Document Revision History (Part 1 of 3)
Errata Sheet for Stratix IV GX Devices
March 2011
December 2010
October 2010
Date
DPA Misalignment
f
1
Version
Update your design in the ALTGX MegaWizard Plug-In Manager in the Quartus II
software version 9.0 and recompile the design. In some cases, you may have to change
your ALTGX input reference frequency, which can be done using the available GPLL
resources or external clock inputs.
Stratix IV GX DPA circuitry for ES devices occasionally become stuck at the initial
configured phase or take significantly longer than expected to select the optimum
phase. A non-ideal phase may result in data bit errors, even after the DPA lock signal
has gone high. Resetting the DPA circuit may not alleviate the problem; in fact,
resetting it might trigger the problem. LVDS receivers configured in DPA mode are
affected. LVDS receivers configured in Soft CDR mode with 0 PPM difference
(synchronous interface) are also affected.
For applications with flexibility in the choice of training patterns, Altera recommends
you choose bit sequences with more data transitions and a non-cyclical pattern similar
to a PRBS or K28.5 code sequence.
For applications using a fixed, cyclical, or data transition sparse training pattern (for
example, if you are using the SPI 4.2 protocol, which specifies a training pattern of
ten 0s and ten 1s), turn on the DPA PLL Calibration feature (available in the
Quartus II software version 9.0) in the ALTLVDS MegaWizard Plug-In Manager.
There are two caveats when enabling the DPA PLL Calibration feature:
■
■
For more information about the DPA PLL Calibration feature, refer to the
Transmitter/Receiver (ALTLVDS) Megafunction User Guide
corresponding to the Quartus II software version 9.0. Until the User Guide is updated,
in the interim, contact Altera’s mySupport at www.mysupport.altera.com.
Table 9
5.7
5.6
5.5
PLL merging (merging RX and RX or merging RX and TX PLL) is not
automatically supported by the ALTLVDS megafunction; use the external PLL
option to handle PLL merging separately.
Timing for all PLL outputs is pulled in by 1/4 of the voltage controlled oscillator
(VCO) phase during the PLL calibration process. This must be taken into account
for external I/O pin timing interfaces and for clock domain transfers (without a
FIFO) when the clocks are not all from this same PLL.
Updated the “I/O Jitter” section of
Added the “PCI Express (PCIe) Gen2 Protocol Link Establishment Issue” section.
■
lists the revision history for this Errata Sheet.
Added the “Quartus II Software Incorrect Setting for Transceiver CDR in All Modes Except
PCIe Mode” and “Dynamic Reconfiguration Issue Between PCIe Mode and Any Other
Transceiver Mode” sections.
Table
1.
Changes
planned release
March 2011 Altera Corporation
Document Revision History
SERDES