EP4SGX530KH40C2N Altera, EP4SGX530KH40C2N Datasheet - Page 7

• Manufacturer Part Number: EP4SGX530KH40C2N
• Description: IC STRATIX IV FPGA 530K 1517HBGA
• Manufacturer: Altera
• Series: Stratix® IV GXr

Specifications of EP4SGX530KH40C2N

• Number Of Logic Elements/cells: 531200
• Number Of Labs/clbs: 21248
• Total Ram Bits: 27376
• Number Of I /o: 744
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 1517-HBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -

Production Devices for Stratix IV GX Devices
March 2011 Altera Corporation
M144K RAM Block Lock-Up
1
Use the calibration block clock (cal_blk_clk) for the pll_locked_soft_logic module.
The cal_blk_clk frequency specification ranges from 10 MHz to 125 MHz.
Depending on your cal_blk_clk frequency, set the parameter p_delay_counter in the
pll_locked_soft_logic so that the delay is equal to 100 μs (worst-case transmitter
PLL lock time).
M144K blocks may lock up if there is a glitch in the clock source when rden equals 1.
In the lock-up state, the RAM block does not respond to read or write operations and
requires an FPGA reconfiguration to restore operation. The issue occurs within the
M144K RAM in the Read Timer Trigger circuitry. A clock glitch may inadvertently
freeze the Read Timer Trigger circuitry, locking the RAM block in its last operation.
MLABs and M9K RAM blocks are not affected.
The workaround is to add clock-enable logic, an internal PLL, or clock-generation
logic (for example, a clock divider). You can add clock-enable logic (internal or
external) to disable the RAM block operation until the clock is stable. You can also
gate the clock internally or externally. If FPGA resources permit, you can use an
internal PLL or clock-generation logic to ensure a stable clock source at the RAM
block input.
The Read Timer circuitry makes RAM block operation independent of the input clock
duty cycle, thus maximizing design performance. If you cannot provide a stable clock,
use the DCD option in the Quartus II software version 9.1 to work around this
problem. When the M144K block uses the DCD option, it does not exhibit the lock-up
behavior, but clock high-time requirements are increased and f
degraded.
If you cannot provide a stable clock input without glitches, perform the following
steps to enable the DCD option in the Quartus II software:
1. On the Assignments menu, click Settings.
2. In the Category list, select Fitter Settings.
3. Click More Settings.
4. Under Existing option settings, set M144K Block Read Clock Duty Cycle
5. Click OK.
6. Compile your design.
There is a .qsf variable that you can use instead of the previous instructions for
making a global assignment.
DCD is on globally by adding the following line to the project’s .qsf (the default is
Off):
set_global_assignment -name M144K_BLOCK_READ_CLOCK_DUTY_CYCLE_DEPENDENCY
ON
Alternatively, you can also apply this setting to individual M144K blocks with the
Assignment Editor.
Global and per instance assignments can be mixed. For example, you can set DCD to
On globally, but set it to Off for an instance. You can also only set it to On by instance.
Dependency to On.
Errata Sheet for Stratix IV GX Devices
M AX
performance is
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