XC3S50-4VQG100I Xilinx Inc, XC3S50-4VQG100I Datasheet - Page 132

• Manufacturer Part Number: XC3S50-4VQG100I
• Description: SPARTAN-3A FPGA 50K STD 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S50-4VQG100I

• Total Ram Bits: 73728
• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 192
• Number Of I /o: 63
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• No. Of Logic Blocks: 192
• No. Of Gates: 50000
• No. Of Macrocells: 1728
• Family Type: Spartan-3
• No. Of Speed Grades: 4
• No. Of I/o's: 63
• Clock Management: DLL
• Package: 100VTQFP
• Family Name: Spartan®-3
• Device Logic Units: 1728
• Device System Gates: 50000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 63
• Ram Bits: 73728
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: Pinout Descriptions
Table 90: TQ144 Package Pinout (Continued)
132
Bank
0,1
0,1
0,1
2,3
2,3
5
5
5
5
5
5
5
5
6
6
6
6
6
6
6
6
6
6
6
6
6
6
7
7
7
7
7
7
7
7
7
7
7
7
7
7
7
IO_L01N_5/RDWR_B
IO_L01P_5/CS_B
IO_L28N_5/D6
IO_L28P_5/D7
IO_L31N_5/D4
IO_L31P_5/D5
IO_L32N_5/GCLK3
IO_L32P_5/GCLK2
IO_L01N_6/VRP_6
IO_L01P_6/VRN_6
IO_L20N_6
IO_L20P_6
IO_L21N_6
IO_L21P_6
IO_L22N_6
IO_L22P_6
IO_L23N_6
IO_L23P_6
IO_L24N_6/VREF_6
IO_L24P_6
IO_L40N_6
IO_L40P_6/VREF_6
IO/VREF_7
IO_L01N_7/VRP_7
IO_L01P_7/VRN_7
IO_L20N_7
IO_L20P_7
IO_L21N_7
IO_L21P_7
IO_L22N_7
IO_L22P_7
IO_L23N_7
IO_L23P_7
IO_L24N_7
IO_L24P_7
IO_L40N_7/VREF_7
IO_L40P_7
VCCO_TOP
VCCO_TOP
VCCO_TOP
VCCO_RIGHT
VCCO_RIGHT
Pin Name
XC3S200
XC3S400
XC3S50
TQ144 Pin
Number
P126
P138
P115
P106
P41
P40
P47
P46
P51
P50
P53
P52
P36
P35
P33
P32
P31
P30
P28
P27
P26
P25
P24
P23
P21
P20
P11
P10
P13
P12
P15
P14
P18
P17
P75
P4
P2
P1
P6
P5
P8
P7
VCCO
VCCO
VCCO
VCCO
VCCO
GCLK
GCLK
DUAL
DUAL
DUAL
DUAL
DUAL
DUAL
VREF
VREF
VREF
VREF
Type
DCI
DCI
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
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Table 90: TQ144 Package Pinout (Continued)
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCAUX
Bank
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
2,3
4,5
4,5
4,5
6,7
6,7
6,7
VCCO_RIGHT
VCCO_BOTTOM
VCCO_BOTTOM
VCCO_BOTTOM
VCCO_LEFT
VCCO_LEFT
VCCO_LEFT
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCINT
CCLK
DONE
HSWAP_EN
M0
M1
M2
PROG_B
TCK
TDI
TDO
TMS
Pin Name
XC3S200
XC3S400
XC3S50
DS099-4 (v2.5) December 4, 2009
TQ144 Pin
Product Specification
Number
P136
P139
P114
P117
P101
P134
P120
P133
P121
P142
P143
P110
P144
P109
P111
P91
P54
P43
P66
P19
P34
P94
P81
P88
P64
P67
P42
P45
P22
P29
P16
P62
P48
P61
P49
P72
P71
P38
P37
P39
P3
P9
VCCAUX
VCCAUX
VCCAUX
VCCAUX
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
VCCINT
VCCINT
VCCINT
VCCINT
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
VCCO
JTAG
JTAG
JTAG
JTAG
Type
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
R