XC3S50-4VQG100I Xilinx Inc, XC3S50-4VQG100I Datasheet - Page 90

• Manufacturer Part Number: XC3S50-4VQG100I
• Description: SPARTAN-3A FPGA 50K STD 100-VQFP
• Manufacturer: Xilinx Inc
• Series: Spartan™-3r

Specifications of XC3S50-4VQG100I

• Total Ram Bits: 73728
• Number Of Logic Elements/cells: 1728
• Number Of Labs/clbs: 192
• Number Of I /o: 63
• Number Of Gates: 50000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 100-TQFP
• No. Of Logic Blocks: 192
• No. Of Gates: 50000
• No. Of Macrocells: 1728
• Family Type: Spartan-3
• No. Of Speed Grades: 4
• No. Of I/o's: 63
• Clock Management: DLL
• Package: 100VTQFP
• Family Name: Spartan®-3
• Device Logic Units: 1728
• Device System Gates: 50000
• Maximum Internal Frequency: 630 MHz
• Typical Operating Supply Voltage: 1.2 V
• Maximum Number Of User I/os: 63
• Ram Bits: 73728
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Spartan-3 FPGA Family: DC and Switching Characteristics
Phase Shifter (PS)
Phase shifter operation is only supported if the DLL is in low-frequency mode, see
software version 10.1.03 (or later).
Table 61: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 62: Switching Characteristics for the PS in Variable or Fixed Phase Shift Mode
90
Notes:
1.
2.
Operating Frequency Ranges
PSCLK_FREQ
(F
Input Pulse Requirements
PSCLK_PULSE
Phase Shifting Range
FINE_SHIFT_RANGE
Lock Time
LOCK_DLL_PS
LOCK_DLL_PS_FX
PSCLK
The numbers in this table are based on the operating conditions set forth in
The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE or FIXED.
Symbol
Symbol
)
Frequency for the
PSCLK input
PSCLK pulse width
as a percentage of
the PSCLK period
Description
Phase shift range
When using the PS in conjunction
with the DLL: The time from
deassertion at the DCM’s Reset
input to the rising transition at its
LOCKED output. When the DCM
is locked, the CLKIN and CLKFB
signals are in phase.
When using the PS in conjunction
with the DLL and DFS: The time
from deassertion at the DCM’s
Reset input to the rising transition
at its LOCKED output. When the
DCM is locked, the CLKIN and
CLKFB signals are in phase.
Description
Low
Frequency Mode/
F
CLKIN
F
F
Low
CLKIN
CLKIN
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Range
60 MHz < F
18 MHz < F
30 MHz < F
40 MHz < F
50 MHz < F
< 100 MHz
> 100 MHz
Frequency Mode/
F
CLKIN
CLKIN
Low
CLKIN
CLKIN
CLKIN
CLKIN
Low
Range
< 165 MHz
< 30 MHz
< 40 MHz
< 50 MHz
< 60 MHz
40%
45%
Table 31
Min
1
-5
and
Table
60%
55%
Max
167
Speed Grade
Table
Min
-
-
-
-
-
-
-
57. Fixed phase shift requires ISE
-5
61.
DS099-3 (v2.5) December 4, 2009
10.40
Speed Grade
Max
10.0
3.28
2.56
1.60
1.00
0.88
40%
45%
Min
1
-4
Min
Product Specification
-
-
-
-
-
-
-
60%
55%
Max
167
-4
10.40
Max
10.0
3.28
2.56
1.60
1.00
0.88
Units
MHz
Units
-
-
ms
ms
ms
ms
ms
ms
ns
R