XC3S1200E-4FGG320I Xilinx Inc, XC3S1200E-4FGG320I Datasheet - Page 147
![IC FPGA SPARTAN-3E 1200K 320FBGA](/photos/6/72/67295/pk071-320_sml.jpg)
XC3S1200E-4FGG320I
Manufacturer Part Number
XC3S1200E-4FGG320I
Description
IC FPGA SPARTAN-3E 1200K 320FBGA
Manufacturer
Xilinx Inc
Series
Spartan™-3Er
Datasheet
1.XC3S100E-4VQG100C.pdf
(233 pages)
Specifications of XC3S1200E-4FGG320I
Number Of Logic Elements/cells
19512
Number Of Labs/clbs
2168
Total Ram Bits
516096
Number Of I /o
250
Number Of Gates
1200000
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
320-BGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC3S1200E-4FGG320I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC3S1200E-4FGG320I
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
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Table 107: Switching Characteristics for the DFS (Continued)
Notes:
1.
2.
3.
4.
5.
6.
Phase Shifter (PS)
Table 108: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 109: Switching Characteristics for the PS in Variable Phase Mode
DS312-3 (v3.8) August 26, 2009
Product Specification
Lock Time
LOCK_FX
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX
Operating Frequency Ranges
PSCLK_FREQ
(F
Input Pulse Requirements
PSCLK_PULSE
PSCLK
The numbers in this table are based on the operating conditions set forth in
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (150 ps input period jitter, 40 SSOs and 25% CLB
switching). Output jitter strongly depends on the environment, including the number of SSOs, the output drive strength, CLB
utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual maximum output jitter depends on
the system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include 1% of the CLKFX output period or 0.01 UI. Example: The data sheet specifies
a maximum jitter of "±[1% of CLKFX period + 300]". Assume the CLKFX output frequency is 100 MHz. The equivalent CLKFX period
is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the maximum jitter is ±[100 ps + 300 ps] = ±400 ps.
Use the Spartan-3A Jitter Calculator (www.xilinx.com/support/documentation/data_sheets/s3a_jitter_calc.zip) to estimate DFS output jitter.
Use the Clocking Wizard to determine jitter for a specific design.
Symbol
)
(2)
Symbol
Symbol
R
(2)
Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts
LOCKED when the CLKFX and
CLKFX180 signals are valid. If using
both the DLL and the DFS, use the
longer locking time.
Maximum allowed number of DCM_DELAY_STEP
steps for a given CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE, double the effective
clock period.
Minimum guaranteed delay for variable phase shifting
Maximum guaranteed delay for variable phase shifting
Description
Description
Description
www.xilinx.com
F
F
5 MHz <
15 MHz
15 MHz
CLKIN
CLKIN
<
>
Table 77
Device
All
and
40%
CLKIN < 60 MHz
CLKIN > 60 MHz
Min
1
Table
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
DC and Switching Characteristics
-5
Min
-
-
60%
±[MAX_STEPS •
±[MAX_STEPS •
106.
Max
Speed Grade
167
-5
Equation
Speed Grade
Max
450
5
40%
±[INTEGER(10 •
±[INTEGER(15 •
(T
(T
Min
1
CLKIN
CLKIN
Min
-
-
-4
– 3 ns))]
– 3 ns))]
-4
Max
60%
167
Max
450
5
Units
MHz
Units
steps
steps
Units
ns
ns
ms
μs
-
147
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