XA3S700A-4FGG400I Xilinx Inc, XA3S700A-4FGG400I Datasheet - Page 42

• Manufacturer Part Number: XA3S700A-4FGG400I
• Description: IC FPGA SPARTAN-3A 700K 400-FBGA
• Manufacturer: Xilinx Inc
• Series: Spartan™-3A XAr

Specifications of XA3S700A-4FGG400I

• Number Of Logic Elements/cells: 13248
• Number Of Labs/clbs: 1472
• Total Ram Bits: 368640
• Number Of I /o: 311
• Number Of Gates: 700000
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 400-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 38: Switching Characteristics for the DFS (Continued)
Notes:
1.
2.
3.
4.
5.
6.
Phase Shifter
Table 39: Recommended Operating Conditions for the PS in Variable Phase Mode
Table 40: Switching Characteristics for the PS in Variable Phase Mode
Notes:
1.
2.
3.
42
Lock Time
LOCK_FX
Phase Shifting Range
MAX_STEPS
FINE_SHIFT_RANGE_MIN
FINE_SHIFT_RANGE_MAX
Operating Frequency Ranges
PSCLK_FREQ
(F
Input Pulse Requirements
PSCLK_PULSE
PSCLK
The numbers in this table are based on the operating conditions set forth in
DFS performance requires the additional logic automatically added by ISE 9.1i and later software revisions.
For optimal jitter tolerance and faster lock time, use the CLKIN_PERIOD attribute.
Maximum output jitter is characterized within a reasonable noise environment (40 SSOs and 25% CLB switching) on an
XC3S1400A FPGA. Output jitter strongly depends on the environment, including the number of SSOs, the output drive
strength, CLB utilization, CLB switching activities, switching frequency, power supply and PCB design. The actual
maximum output jitter depends on the system application.
The CLKFX and CLKFX180 outputs always have an approximate 50% duty cycle.
Some duty-cycle and alignment specifications include a percentage of the CLKFX output period. For example, the data
sheet specifies a maximum CLKFX jitter of “±[1% of CLKFX period + 200]”. Assume the CLKFX output frequency is 100
MHz. The equivalent CLKFX period is 10 ns and 1% of 10 ns is 0.1 ns or 100 ps. According to the data sheet, the
maximum jitter is ±[100 ps + 200 ps] = ±300 ps.
The numbers in this table are based on the operating conditions set forth in
The maximum variable phase shift range, MAX_STEPS, is only valid when the DCM is has no initial fixed phase shifting, that is, the
PHASE_SHIFT attribute is set to 0.
The DCM_DELAY_STEP values are provided at the bottom of
Symbol
)
(2, 3)
Symbol
Symbol
(2)
Frequency for the PSCLK input
PSCLK pulse width as a percentage of the PSCLK period
The time from deassertion at the DCM’s
Reset input to the rising transition at its
LOCKED output. The DFS asserts LOCKED
when the CLKFX and CLKFX180 signals are
valid. If using both the DLL and the DFS, use
the longer locking time.
Maximum allowed number of
DCM_DELAY_STEP steps for a given
CLKIN clock period, where T = CLKIN
clock period in ns. If using
CLKIN_DIVIDE_BY_2 = TRUE,
double the clock effective clock
period.
Minimum guaranteed delay for variable phase shifting
Maximum guaranteed delay for variable phase shifting
Description
Description
Description
www.xilinx.com
Table
F
5 MHz < F
CLKIN < 60 MHz
CLKIN
CLKIN
36.
< 15 MHz
Table 8
> 15 MHz
≥
CLKIN
Table 8
60 MHz
and
Device
Table
and
All
40%
Min
Speed Grade
1
±[INTEGER(10 • (T
±[INTEGER(15 • (T
Table
37.
DCM_DELAY_STEP_MAX]
DCM_DELAY_STEP_MIN]
-4
Speed Grade
Min
–
–
39.
Phase Shift Amount
60%
Max
167
±[MAX_STEPS •
±[MAX_STEPS •
-4
DS681 (v1.1) February 3, 2009
Max
450
5
Units
MHz
–
CLKIN
CLKIN
Units
Product Specification
ms
μs
– 3 ns))]
– 3 ns))]
steps
Units
ns
ns
R