XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 48
![IC FPGA VIRTEX-4 FX 20K 672-FBGA](/photos/19/4/190420/4579314_sml.jpg)
XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
ADVANTEK
Quantity:
314
Company:
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
Table 58: Global Clock Setup and Hold for LVCMOS25 Standard, without DCM
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
3.
Input Setup and Hold Time Relative to Global Clock Input Signal for LVCMOS25 Standard.
T
PSFD
Setup time is measured relative to the Global Clock input signal with the fastest route and the lightest load. Hold time is measured relative to the
Global Clock input signal with the slowest route and heaviest load.
IFF = Input Flip-Flop or Latch.
A Zero “0” Hold Time listing indicates no hold time or a negative hold time. Negative values cannot be guaranteed “best-case,” but if a “0” is listed,
there is no positive hold time.
Symbol
/ T
PHFD
Full Delay
Global Clock and IFF
Description
(2)
without DCM
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
XC4VLX100
XC4VLX160
XC4VLX200
XC4VFX100
XC4VFX140
XC4VSX25
XC4VSX35
XC4VSX55
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
Device
(1)
–0.09
1.82
0.11
1.79
0.20
2.06
0.13
2.39
0.04
2.36
0.16
4.85
2.56
0.46
2.12
0.14
2.10
0.21
1.99
0.57
1.82
0.12
1.75
0.38
1.82
0.64
2.42
0.25
1.99
1.11
N/A
N/A
-12
Speed Grade
–0.09
2.33
0.19
2.30
0.29
2.61
0.22
2.99
0.12
2.96
0.26
5.83
3.21
0.59
3.57
0.64
2.68
0.23
2.66
0.30
2.53
0.71
2.33
0.20
2.26
0.49
2.34
0.78
3.03
0.35
2.21
1.31
2.80
1.26
-11
–0.01
2.74
0.39
2.70
0.50
3.06
0.44
3.50
0.34
3.47
0.49
6.76
3.76
0.88
4.17
0.95
3.14
0.44
3.12
0.52
2.97
0.98
2.73
0.39
2.65
0.73
2.75
1.05
3.54
0.59
2.60
1.64
3.28
1.61
-10
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
48