XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 49

• Manufacturer Part Number: XC4VFX20-10FFG672C
• Description: IC FPGA VIRTEX-4 FX 20K 672-FBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-4r

Specifications of XC4VFX20-10FFG672C

• Total Ram Bits: 1253376
• Number Of Logic Elements/cells: 19224
• Number Of Labs/clbs: 2136
• Number Of I /o: 320
• Voltage - Supply: 1.14 V ~ 1.26 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 672-BBGA, FCBGA
• No. Of Logic Blocks: 19224
• No. Of Macrocells: 19224
• No. Of Speed Grades: 10
• No. Of I/o's: 320
• Clock Management: DCM
• I/o Supply Voltage: 3.45V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ChipSync™ Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-4 FPGA
source-synchronous transmitter and receiver data-valid windows.
Table 59: Duty Cycle Distortion and Clock-Tree Skew
DS302 (v3.7) September 9, 2009
Product Specification
Notes:
1.
2.
T
T
T
T
T
T
T
DCD_CLK
CKSKEW
DCD_BUFIO
BUFIOSKEW
DCD_BUFR
BUFIO_MAX_FREQ
BUFR_MAX_FREQ
These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For cases where
other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.
The T
skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor and Timing
Analyzer tools to evaluate clock skew specific to your application.
Symbol
CKSKEW
value represents the worst-case vertical clock-tree skew observable between sequential I/O elements. Significantly less clock-tree
Global Clock Tree Duty Cycle Distortion
Global Clock Tree Skew
I/O clock tree duty cycle distortion
I/O clock tree skew across one clock region
I/O clock tree skew across multiple clock regions
Regional clock tree duty cycle distortion
I/O clock tree MAX frequency
Regional clock tree MAX frequency
Description
(2)
www.xilinx.com
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(1)
XC4VLX100
XC4VLX160
XC4VLX200
XC4VFX100
XC4VFX140
XC4VLX15
XC4VLX25
XC4VLX40
XC4VLX60
XC4VLX80
XC4VSX25
XC4VSX35
XC4VSX55
XC4VFX12
XC4VFX20
XC4VFX40
XC4VFX60
Device
All
All
All
All
All
All
All
-12
150
140
140
200
270
270
N/A
140
140
200
N/A
100
250
710
300
50
90
50
90
50
60
90
50
50
Speed Grade
-11
150
100
160
160
230
310
310
310
100
170
110
170
230
310
100
250
710
250
60
60
60
70
50
50
150
110
180
180
260
350
350
350
120
190
120
190
260
350
100
250
645
250
-10
60
70
70
70
50
50
Units
MHz
MHz
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
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