XC4VFX20-10FFG672C Xilinx Inc, XC4VFX20-10FFG672C Datasheet - Page 56
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XC4VFX20-10FFG672C
Manufacturer Part Number
XC4VFX20-10FFG672C
Description
IC FPGA VIRTEX-4 FX 20K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Datasheets
1.XC4VFX12-10FFG668C.pdf
(58 pages)
2.XC4VFX12-10FFG668C.pdf
(9 pages)
3.XC4VFX12-10FFG668C.pdf
(406 pages)
Specifications of XC4VFX20-10FFG672C
Total Ram Bits
1253376
Number Of Logic Elements/cells
19224
Number Of Labs/clbs
2136
Number Of I /o
320
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
No. Of Logic Blocks
19224
No. Of Macrocells
19224
No. Of Speed Grades
10
No. Of I/o's
320
Clock Management
DCM
I/o Supply Voltage
3.45V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
HW-V4-ML405-UNI-G - EVALUATION PLATFORM VIRTEX-4
Number Of Gates
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
ADVANTEK
Quantity:
314
Company:
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XilinxInc
Quantity:
3 000
Company:
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX20-10FFG672C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
DS302 (v3.7) September 9, 2009
Product Specification
12/11/06
03/27/07
06/08/07
08/10/07
09/10/07
(Cont’d)
Date
Version
(Cont’d)
2.0
2.1
2.2
2.3
2.4
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Table
Table
Table
SPEED SPECIFICATION version for this data sheet release: v1.64.
Table
Table
Table
Clocking frequency. Corrected “Conditions”.
Table
Table
Table
and -12 values for T
Table
new parameter T
Table
parameters from earlier revision. Added Notes (4) through (7) to these parameters.
Table
Table
SPEED SPECIFICATION version for this data sheet release: v1.65.
Table
XC4VFX60 to Production status.
Table
be connected to GND.
Table
external configuration clock frequency.
Table
Table
SPEED SPECIFICATION version for this data sheet release: v1.65.
Table
Table
Table
UG070.
Added section
Table
Added section
including
Table
SelectMAP Setup/Hold.
Table
longer needed.
SPEED SPECIFICATION version for this data sheet release: v1.67.
Table
XC4VFX100 devices, to Production status.
Table
Table
50: Removed T_LOCK_FX_MIN parameter. Added DCM_RESET.
53: Added Note (1), no minimum frequency for PMCD.
64: Added Note (1) to refer to LX and SX Errata for capability improvements.
4: Added Note (6) regarding max quiescent supply current.
5: Filled in missing power-on current values for FX devices.
24: Added new parameter F
26: Revised Notes (2) and (3).
37,
39: Added columns/values for XC4VFX -11 and -12. Corrected XC4VLX/SX -11
43: Restored parameter T
50: Restored DCM_RESET Minimum and DCM_INPUT_CLOCK_STOP
60: Removed FF1760 package. Not supported.
63: Added FX devices and JTAG IDs.
14: Promoted -12 speed grade devices of XC4VFX12, XC4VFX20, and
37: Removed parameter T
43: Added parameter F
63: Filled in Step 1 values for XC4VFX20, XC4VFX60, and XC4VFX100.
65: Added Step 1 data.
3: Added MAX value for I
25: Added unit (ns) to RXSIGDET.
27: Added Note (3) specifying range of DCI reference resistors and referring to
29.
43: Added parameter F
64: Added to Capability Improvements, for Step 1 that the DFS macro is no
14: Promoted all speed grades for XC4VFX40 devices, and -12 speed grade for
63: Filled in Step 1 value for XC4VFX40.
65: Added Note 1.
Table
Table
Ethernet MAC Switching Characteristics, page
I/O Standard Adjustment Measurement Methodology, page
30,
38: Added column/values for XC4VFX -12.
SMCO
www.xilinx.com
Table
REGXB
Virtex-4 FPGA Data Sheet: DC and Switching Characteristics
(SelectMAP Readback Clock-to-Out).
31, and
, T
REGYB
MAX_SELECTMAP
MAX_ICAP
BATT
CONFIG
ISCCK_REV
Figure
GREFCLK
, and T
.
Revisions
. Added word “Data” to description of
and footnote (1) from earlier revision. Added
4.
CKSH
. Not meaningful because pin should always
. Added Min value for Spread Spectrum
. for maximum Slave SelectMAP mode
.
22, and replaced
23,
56