XC4VFX40-11FFG672I Xilinx Inc, XC4VFX40-11FFG672I Datasheet - Page 149

no-image

XC4VFX40-11FFG672I

Manufacturer Part Number
XC4VFX40-11FFG672I
Description
IC FPGA VIRTEX-4 FX 40K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r

Specifications of XC4VFX40-11FFG672I

Number Of Logic Elements/cells
41904
Number Of Labs/clbs
4656
Total Ram Bits
2654208
Number Of I /o
352
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
672-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
XC4VFX40-11FFG672I
Manufacturer:
AD
Quantity:
967
Part Number:
XC4VFX40-11FFG672I
Manufacturer:
XilinxInc
Quantity:
3 000
Part Number:
XC4VFX40-11FFG672I
Manufacturer:
Xilinx Inc
Quantity:
10 000
Part Number:
XC4VFX40-11FFG672I
Manufacturer:
XILINX
0
Top-Level View of FIFO Architecture
FIFO Primitive
Virtex-4 FPGA User Guide
UG070 (v2.6) December 1, 2008
R
Figure 4-14
write pointer, and status flag logic are dedicated for FIFO use only.
Figure 4-15
wrcount
shows a top-level view of the Virtex-4 FIFO architecture. The read pointer,
shows the FIFO16 primitive.
wrclk
reset
wren
DIN
Figure 4-14: Top-Level View of FIFO in Block RAM
Pointer
Write
www.xilinx.com
Figure 4-15: FIFO16 Primitive
DI[31:0]
DIP[3:0]
RDEN
RDCLK
WREN
WRCLK
RST
waddr
Status Flag
Block RAM
FIFO16
Logic
Core
WRCOUNT[11:0]
ALMOSTEMPTY
RDCOUNT[11:0]
ALMOSTFULL
DOP[3:0]
DO[31:0]
WRERR
Top-Level View of FIFO Architecture
RDERR
EMPTY
FULL
raddr
ug070_4_15_071204
Pointer
Read
UG070_4_14_030708
rdcount
DO
rdclk
rden
149

Related parts for XC4VFX40-11FFG672I