XC5VSX50T-1FFG665C Xilinx Inc, XC5VSX50T-1FFG665C Datasheet - Page 204

• Manufacturer Part Number: XC5VSX50T-1FFG665C
• Description: IC FPGA VIRTEX-5 50K 665-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665C

• Total Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• No. Of Logic Blocks: 8160
• No. Of Gates: 50000
• Family Type: Virtex-5 SXT
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1568

Chapter 5: Configurable Logic Blocks (CLBs)
204
Slice Distributed RAM Timing Model and Parameters (Available in
SLICEM only)
Figure 5-27
slice. Some elements of the slice are omitted for clarity. Only the elements relevant to the
timing paths described in this section are shown.
X-Ref Target - Figure 5-27
Figure 5-27: Simplified Virtex-5 FPGA SLICEM Distributed RAM
illustrates the details of distributed RAM implemented in a Virtex-5 FPGA
D input
C input
B input
A input
CLK
WE
DX
CX
BX
AX
DI
CI
BI
AI
www.xilinx.com
6
6
6
6
DI1
DI2
A[6:0]
WA[6:0]
CLK
WE
DI1
DI2
A[6:0]
WA[6:0]
CLK
WE
DI1
DI2
A[6:0]
WA[6:0]
CLK
WE
DI1
DI2
A[6:0]
WA[6:0]
CLK
WE
RAM
RAM
RAM
RAM
O6
O5
O6
O5
O6
O5
O6
O5
UG190_5_27_050506
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
D
DMUX
C
CMUX
B
BMUX
A
AMUX