XC5VSX50T-1FFG665C Xilinx Inc, XC5VSX50T-1FFG665C Datasheet - Page 221

• Manufacturer Part Number: XC5VSX50T-1FFG665C
• Description: IC FPGA VIRTEX-5 50K 665-FCBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-5 SXTr

Specifications of XC5VSX50T-1FFG665C

• Total Ram Bits: 4866048
• Number Of Logic Elements/cells: 52224
• Number Of Labs/clbs: 4080
• Number Of I /o: 360
• Voltage - Supply: 0.95 V ~ 1.05 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 665-BBGA, FCBGA
• No. Of Logic Blocks: 8160
• No. Of Gates: 50000
• Family Type: Virtex-5 SXT
• No. Of Speed Grades: 1
• No. Of I/o's: 360
• Clock Management: PLL
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: HW-V5-ML506-UNI-G - EVALUATION PLATFORM VIRTEX-5
• Number Of Gates: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 122-1568

Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
without connecting the VRN/VRP pins on these banks to external resistors. DCI
impedance control in cascaded banks is received from the master bank.
When using DCI cascading, the DCI control circuitry in the master bank creates and routes
DCI control to the cascaded banks in daisy-chain style. Only the master bank’s VRN/VRP
pins are required when using DCI cascading.
Also, when using DCI cascading, only one set of VRN/VRP pins provides the DCI
reference voltage for multiple banks. DCI cascading:
•
•
•
Similarly, due to the center column architecture, the half-size banks 1, 2, 3, and 4 are
separated from all the other banks in the center column by the CMT tiles. It is not possible
to cascade across the CMT tiles. This affects the larger devices that have more than four
user I/O center column banks (plus bank 0). For instance, bank 4 cannot be cascaded with
bank 6, and bank 3 cannot be cascaded with bank 5. Bank 3 can only be cascaded with bank
1, and bank 4 can only be cascaded with bank 2.
Figure 6-5
Reduces overall power, since fewer voltage references are required
Frees up VRN/VRP pins on slave banks for general customer use
DCI in banks 1 and 2 is supported only through cascading. These two banks do not
have VRN/VRP pins and therefore cannot be used as master or stand-alone DCI
banks. Cascading is not possible through bank 0.
shows DCI cascading support over multiple banks. Bank B is the master bank.
www.xilinx.com
SelectIO Resources General Guidelines
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