XC4VFX60-11FFG672C Xilinx Inc, XC4VFX60-11FFG672C Datasheet - Page 212
XC4VFX60-11FFG672C
Manufacturer Part Number
XC4VFX60-11FFG672C
Description
IC FPGA VIRTEX-4 FX 60K 672-FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-4r
Specifications of XC4VFX60-11FFG672C
Number Of Logic Elements/cells
56880
Number Of Labs/clbs
6320
Total Ram Bits
4276224
Number Of I /o
352
Voltage - Supply
1.14 V ~ 1.26 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
672-BBGA, FCBGA
For Use With
HW-V4-ML410-UNI-G - EVALUATION PLATFORM VIRTEX-4
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 5: Configurable Logic Blocks (CLBs)
Table 5-7: Slice SRL Timing Parameters
212
Sequential Delays for Slice LUT Configured as SRL (Select Shift Register)
T
T
T
T
T
Setup/Hold Times for Slice LUT Configured as SRL (Select Shift Register)
T
T
T
T
T
T
Parameter
REG
CKSH
REGF5
REGXB
REGYB
xxS
xxH
WS
WH
DS
DH
/
/
= Setup time (before clock edge)
= Hold time (after clock edge)
/
CLK to X/Y outputs
CLK to Shift_out
CLK to F5 output
CLK to XB/YB outputs
CE input (WE)
BX/BY configured as data
input (DI)
Slice SRL Timing Parameters
Slice SRL Timing Characteristics
Table 5-7
Figure
Figure 5-25
Virtex-4 FPGA slice (LUT configured as SRL).
Function
MSB (MC15)
Write Enable
Data Out (D)
Shift_In (DI)
Address
5-24.
(SR)
CLK
T
REGXB
shows the SLICEM SRL timing parameters for a majority of the paths in
illustrates the timing characteristics of a 16-bit shift register implemented in a
X
X
1
T
T
0
Figure 5-25: Slice SRL Timing Characteristics
WS
DS
T
Time after the Clock (CLK) of a Write operation that the data written to
the SRL is stable on the X/Y outputs of the slice.
Time after the Clock (CLK) of a Write operation that the data written to
the SRL is stable on the Shift_out or XB/YB outputs of the slice.
Time after the Clock (CLK) of a Write operation that the data written to
the SRL is stable on the F5 output of the slice.
Time after the Clock (CLK) of a Write operation that the data written to
the SRL is stable on the XB/YB outputs of the slice.
The following descriptions are for setup times only.
Time before the clock that the write enable signal must be stable at the
WE input of the slice LUT (configured as SRL).
Time before the clock that the data must be stable at the BX/BY input
of the slice.
REG
0
X
0
www.xilinx.com
2
1
1
X
3
1
1
T
X
ILO
0
4
Description
0
2
X
1
5
UG070 (v2.6) December 1, 2008
1
Virtex-4 FPGA User Guide
T
1
ILO
X
0
6
1
0
1
X
UG070_5_25_080204
16
0
R
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