XCV405E-7BG560I Xilinx Inc, XCV405E-7BG560I Datasheet - Page 20

• Manufacturer Part Number: XCV405E-7BG560I
• Description: IC FPGA 1.8V 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV405E-7BG560I

• Number Of Logic Elements/cells: 10800
• Number Of Labs/clbs: 2400
• Total Ram Bits: 573440
• Number Of I /o: 404
• Number Of Gates: 129600
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
2. Drive data onto D[7:0]. Note that to avoid contention,
Table 11:
A flowchart for the write operation appears in
Note that if CCLK is slower than f
asserts BUSY, In this case, the above handshake is unnec-
essary, and data can simply be entered into the FPGA every
CCLK cycle.
Abort
During a given assertion of CS, the user cannot switch from
a write to a read, or vice-versa. This action causes the cur-
Module 2 of 4
16
CCLK
either asserted or de-asserted. Otherwise an abort is
initiated, as described below.
the data source should not be enabled while CS is Low
and WRITE is High. Similarly, while WRITE is High, no
more that one CS should be asserted.
D
CS Setup/Hold
WRITE Setup/Hold
BUSY Propagation Delay
Maximum Frequency
Maximum Frequency with no handshake
SelectMAP Write Timing Characteristics
0-7
DATA[0:7]
Setup/Hold
WRITE
BUSY
CCLK
CS
Description
5
No Write
3
CCNH
1
, the FPGA never
7
Figure 17: Write Operations
Figure
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Write
18.
2
3. At the rising edge of CCLK: If BUSY is Low, the data is
4. Repeat steps 2 and 3 until all the data has been sent.
5. De-assert CS and WRITE.
1/2
3/4
5/6
rent packet command to be aborted. The device remains
BUSY until the aborted operation has completed. Following
an abort, data is assumed to be unaligned to word bound-
aries, and the FPGA requires a new synchronization word
prior to accepting any new packets.
To initiate an abort during a write operation, de-assert
WRITE. At the rising edge of CCLK, an abort is initiated, as
shown in
7
accepted on this clock. If BUSY is High (from a previous
write), the data is not accepted. Acceptance instead
occurs on the first clock after BUSY goes Low, and the
data must be held until this has happened.
No Write
T
Figure
T
T
SMCSCC
SMCCW
SMDCC
T
Symbol
F
SMCKBY
19.
F
CCNH
CC
/T
/T
/T
SMCCD
SMCCCS
SMWCC
Write
DS025-2 (v2.3) November 19, 2002
4
6
DS022_45_071702
5.0 / 1.7
7.0 / 1.7
7.0 / 1.7
Values
12.0
66
50
MHz, max
MHz, max
ns, max
ns, min
ns, min
ns, min
Units
R