XCV405E-7BG560I Xilinx Inc, XCV405E-7BG560I Datasheet - Page 75

• Manufacturer Part Number: XCV405E-7BG560I
• Description: IC FPGA 1.8V 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV405E-7BG560I

• Number Of Logic Elements/cells: 10800
• Number Of Labs/clbs: 2400
• Total Ram Bits: 573440
• Number Of I /o: 404
• Number Of Gates: 129600
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

DLL Clock Tolerance, Jitter, and Phase Information
All DLL output jitter and phase specifications determined through statistical measurement at the package pins using a clock
mirror configuration and matched drivers.
Revision History
The following table shows the revision history for this document.
DS025-3 (v2.3.2) March 14, 2003
Notes:
1.
2.
3.
4.
5.
6.
Input Clock Period Tolerance
Input Clock Jitter Tolerance (Cycle to Cycle)
Time Required for DLL to Acquire Lock
Output Jitter (cycle-to-cycle) for any DLL Clock Output
Phase Offset between CLKIN and CLKO
Phase Offset between Clock Outputs on the DLL
Maximum Phase Difference between CLKIN and CLKO
Maximum Phase Difference between Clock Outputs on the DLL
03/23/00
08/01/00
09/19/00
Output Jitter is cycle-to-cycle jitter measured on the DLL output clock and is based on a maximum tap delay resolution, excluding
input clock jitter.
Phase Offset between CLKIN and CLKO is the worst-case fixed time difference between rising edges of CLKIN and CLKO,
excluding Output Jitter and input clock jitter.
Phase Offset between Clock Outputs on the DLL is the worst-case fixed time difference between rising edges of any two DLL
outputs, excluding Output Jitter and input clock jitter.
Maximum Phase Difference between CLKIN an CLKO is the sum of Output Jitter and Phase Offset between CLKIN and CLKO,
or the greatest difference between CLKIN and CLKO rising edges due to DLL alone (excluding input clock jitter).
Maximum Phase DIfference between Clock Outputs on the DLL is the sum of Output JItter and Phase Offset between any DLL
clock outputs, or the greatest difference between any two DLL output rising edges sue to DLL alone (excluding input clock jitter).
Add 30% to the value for Industrial grade parts.
Date
R
Version
1.0
1.1
1.2
Description
•
•
Initial Xilinx release.
Accumulated edits and fixes. Upgrade to Preliminary. Preview -8 numbers added.
Reformatted to adhere to corporate documentation style guidelines. Minor changes in
BG560 pin-out table.
In Table 3 (Module 4), FG676 Fine-Pitch BGA — XCV405E, the following pins are no
longer labeled as VREF: B7, G16, G26, W26, AF20, AF8, Y1, H1.
Min values added to Virtex-E Electrical Characteristics tables.
(6)
(2)
(3)
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
(1)
(4)
www.xilinx.com
1-800-255-7778
(5)
Symbol
T
T
T
T
T
T
T
T
OJITCC
PHOOM
PHIOM
IJITCC
PHOO
IPTOL
LOCK
PHIO
Revision
50 - 60 MHz
40 - 50 MHz
30 - 40 MHz
25 - 30 MHz
> 60 MHz
F
CLKIN
CLKDLLHF
Min
-
-
-
-
-
-
-
± 150
± 100
± 140
± 160
± 200
Max
± 60
1.0
20
-
-
-
-
Min
CLKDLL
-
-
-
-
-
-
-
± 300
± 100
± 140
± 160
± 200
Max
± 60
120
1.0
20
25
50
90
Module 3 of 4
Units
ns
ps
µs
µs
µs
µs
µs
ps
ps
ps
ps
ps
19