XCV405E-7BG560I Xilinx Inc, XCV405E-7BG560I Datasheet - Page 21

• Manufacturer Part Number: XCV405E-7BG560I
• Description: IC FPGA 1.8V 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV405E-7BG560I

• Number Of Logic Elements/cells: 10800
• Number Of Labs/clbs: 2400
• Total Ram Bits: 573440
• Number Of I /o: 404
• Number Of Gates: 129600
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 560-LBGA, Metal
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Boundary-Scan Mode
In the boundary-scan mode, configuration is done through
the IEEE 1149.1 Test Access Port. Note that the
DS025-2 (v2.3) November 19, 2002
Figure 18: SelectMAP Flowchart for Write Operations
and start-up sequences complete.
later FPGAs enter start-up phase
first FPGAs enter start-up phase
are released, DONE goes High
FPGA checks data using CRC
and pulls INIT Low on error.
clearing pass and releases
configuration memory.
R
When all DONE pins
FPGA starts to clear
FPGA makes a final
Once per bitstream,
INIT when finished.
releasing DONE.
releasing DONE.
DATA[0:7]
If no errors,
If no errors,
WRITE
BUSY
CCLK
CS
Apply Configuration Byte
Configuration Completed
Disable Data Source
Repeat Sequence A
Enter Data Source
Set WRITE = High
Set WRITE = Low
Set CS = High
Set CS = Low
End of Data?
Apply Power
Release INIT
PROGRAM
from Low
to High
Busy?
INIT?
High
Low
Figure 19: SelectMAP Write Abort Waveforms
Yes
Yes
Low
High
No
No
If used to delay
configuration
On first FPGA
On first FPGA
For any other FPGAs
Sequence A
ds003_17_090602
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
www.xilinx.com
1-800-255-7778
PROGRAM pin must be pulled High prior to reconfiguration.
A Low on the PROGRAM pin resets the TAP controller and
no JTAG operations can be performed.
Abort
DS022_46_071702
Module 2 of 4
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