XCV812E-6BG560C Xilinx Inc, XCV812E-6BG560C Datasheet - Page 65

• Manufacturer Part Number: XCV812E-6BG560C
• Description: IC FPGA 1.8V C-TEMP 560-MBGA
• Manufacturer: Xilinx Inc
• Series: Virtex™-E EMr

Specifications of XCV812E-6BG560C

• Number Of Logic Elements/cells: 21168
• Number Of Labs/clbs: 4704
• Total Ram Bits: 1146880
• Number Of I /o: 404
• Number Of Gates: 254016
• Voltage - Supply: 1.71 V ~ 1.89 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 560-LBGA, Metal
• Dc: 0325
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Calculation of T
T
pad. The values for T
load (Csl) for each I/O standard as listed in
Table 2:
DS025-3 (v2.3.2) March 14, 2003
Notes:
1.
2.
LVTTL Fast Slew Rate, 2mA drive
LVTTL Fast Slew Rate, 4mA drive
LVTTL Fast Slew Rate, 6mA drive
LVTTL Fast Slew Rate, 8mA drive
LVTTL Fast Slew Rate, 12mA drive
LVTTL Fast Slew Rate, 16mA drive
LVTTL Fast Slew Rate, 24mA drive
LVTTL Slow Slew Rate, 2mA drive
LVTTL Slow Slew Rate, 4mA drive
LVTTL Slow Slew Rate, 6mA drive
LVTTL Slow Slew Rate, 8mA drive
LVTTL Slow Slew Rate, 12mA drive
LVTTL Slow Slew Rate, 16mA drive
LVTTL Slow Slew Rate, 24mA drive
LVCMOS2
LVCMOS18
PCI 33 MHZ 3.3 V
PCI 66 MHz 3.3 V
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL2 Class I
SSTL2 Class II
SSTL3 Class I
SSTL3 Class II
CTT
AGP
ioop
I/O parameter measurements are made with the capacitance
values shown above. See the
appropriate terminations.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
is the propagation delay from the O Input of the IOB to the
R
Constants for Use in Calculation of T
Standard
ioop
ioop
are based on the standard capacitive
as a Function of Capacitance
Application Examples
(pF)
Csl
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
35
10
10
20
20
20
30
30
30
30
20
10
Table
0
0
2.
(ns/pF)
Virtex™-E 1.8 V Extended Memory Field Programmable Gate Arrays
0.079
0.044
0.043
0.033
0.086
0.058
0.050
0.048
0.041
0.050
0.050
0.033
0.014
0.017
0.022
0.016
0.014
0.028
0.016
0.029
0.016
0.035
0.037
0.41
0.20
0.13
0.41
0.20
0.10
for
ioop
fl
www.xilinx.com
1-800-255-7778
For other capacitive loads, use the formulas below to calcu-
late the corresponding T
where:
Table 3:
Notes:
1.
2.
LVTTL
LVCMOS2
PCI33_3
PCI66_3
GTL
GTL+
HSTL Class I
HSTL Class III
HSTL Class IV
SSTL3 I & II
SSTL2 I & II
CTT
AGP
LVDS
LVPECL
Standard
T
T
Adjustment section.
C
Input waveform switches between V
Measurements are made at V
Minimum. Worst-case values are reported.
I/O parameter measurements are made with the capacitance
values shown in
appropriate terminations.
I/O standard measurements are reflected in the IBIS model
information except where the IBIS format precludes it.
opadjust
ioop
load
= T
is the capacitive load for the design.
Delay Measurement Methodology
is reported above in the Output Delay
ioop
+ T
V
(0.2xV
1.2 – 0.125
V
V
V
V
V
V
V
1.6 – 0.3
REF
Table 2
REF
REF
REF
REF
REF
REF
REF
V
opadjust
REF
V
0
0
L
–0.75
1
–0.2
–0.2
–0.5
–0.5
–0.5
–1.0
–0.2
CCO
ioop
–
. See the
)
+ (C
.
Per PCI Spec
Per PCI Spec
V
1.2 + 0.125
(0.2xV
V
V
V
V
V
V
V
REF
load
1.6 + 0.3
REF
REF
REF
REF
REF
REF
REF
REF
V
REF
V
2.5
3
H
(Typ), Maximum, and
Application Examples
– C
+0.75
+0.2
+0.2
+0.5
+0.5
+0.5
+1.0
+0.2
1
CCO
L
+
and V
sl
)
) * fl
H
Meas.
Point
1.125
.
V
V
V
V
V
V
V
V
V
1.4
1.2
1.6
REF
REF
REF
REF
REF
REF
REF
REF
REF
Module 3 of 4
(Typ)
V
Spec
AGP
0.80
0.75
0.90
0.90
1.25
Per
1.0
1.5
1.5
REF
for
-
-
-
-
2
9