XC5VSX95T-1FFG1136I Xilinx Inc, XC5VSX95T-1FFG1136I Datasheet - Page 117
![IC FPGA VIRTEX-5 95K 1136FBGA](/photos/6/73/67306/xilinx-_1136-fbga_sml.jpg)
XC5VSX95T-1FFG1136I
Manufacturer Part Number
XC5VSX95T-1FFG1136I
Description
IC FPGA VIRTEX-5 95K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-1FFG1136I
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
Read Operation
Write Operation
Write Modes
Table 4-2: True Dual-Port Names and Descriptions (Continued)
In latch mode, the read operation uses one clock edge. The read address is registered on the
read port, and the stored data is loaded into the output latches after the RAM access time.
When using the output register, the read operation will take one extra latency cycle.
A write operation is a single clock-edge operation. The write address is registered on the
write port, and the data input is stored in memory.
Three settings of the write mode determines the behavior of the data available on the
output latches after a write clock edge: WRITE_FIRST, READ_FIRST, and NO_CHANGE.
Write mode selection is set by configuration. The Write mode attribute can be individually
selected for each port. The default mode is WRITE_FIRST. WRITE_FIRST outputs the
newly written data onto the output bus. READ_FIRST outputs the previously stored data
while new data is being written. NO_CHANGE maintains the output previously
generated by a read operation.
For the simple dual port block RAM and ECC configurations, the Write mode is always
READ_FIRST, and therefore no collision can occur when used in synchronous mode.
Notes:
1. The
CASCADEOUTLAT[A|B]
CASCADEINREG[A|B]
CASCADEOUTREG[A|B]
pins.
Data-In Buses - DI[A|B]<#:0> & DIP[A|B]<#:0>
Port Name
www.xilinx.com
Cascade output pin for 64K x 1 mode when optional output
registers are not enabled
Cascade input for 64K x 1 mode when optional input register
is enabled
Cascade output for 64K x 1 mode when optional output
register is enabled
Synchronous Dual-Port and Single-Port RAMs
section has more information on data parity
Description
117
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