XC5VSX95T-1FFG1136I Xilinx Inc, XC5VSX95T-1FFG1136I Datasheet - Page 194
XC5VSX95T-1FFG1136I
Manufacturer Part Number
XC5VSX95T-1FFG1136I
Description
IC FPGA VIRTEX-5 95K 1136FBGA
Manufacturer
Xilinx Inc
Series
Virtex™-5 SXTr
Datasheets
1.XC5VLX30-1FFG324C.pdf
(91 pages)
2.XC5VLX30-1FFG324C.pdf
(13 pages)
3.XC5VLX30-1FFG324C.pdf
(385 pages)
Specifications of XC5VSX95T-1FFG1136I
Number Of Logic Elements/cells
94208
Number Of Labs/clbs
7360
Total Ram Bits
8994816
Number Of I /o
640
Voltage - Supply
0.95 V ~ 1.05 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
1136-BBGA, FCBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
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Chapter 5: Configurable Logic Blocks (CLBs)
194
X-Ref Target - Figure 5-20
It is possible to create shift registers longer than 128 bits across more than one SLICEM.
However, there are no direct connections between slices to form these shift registers.
Shift Register Data Flow
Shift Operation
The shift operation is a single clock-edge operation, with an active-High clock enable
feature. When enable is High, the input (D) is loaded into the first bit of the shift register.
Each bit is also shifted to the next highest bit position. In a cascadable shift register
configuration, the last bit is shifted out on the M31 output.
The bit selected by the 5-bit address port (A[4:0]) appears on the Q output.
Dynamic Read Operation
The Q output is determined by the 5-bit address. Each time a new address is applied to the
5-input address pins, the new bit position value is available on the Q output after the time
SHIFTIN (D)
A[6:0]
CLK
WE
(WE/CE)
Figure 5-20: 128-bit Shift Register Configuration
(CLK)
5
www.xilinx.com
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
DI1
A[6:2]
CLK
WE
SRL32
SRL32
SRL32
SRL32
MC31
MC31
MC31
MC31
O6
O6
O6
O6
(MC31)
F7BMUX
F7AMUX
CX (A5)
AX (A5)
SHIFTOUT (Q127)
BX (A6)
F8MUX
Virtex-5 FPGA User Guide
UG190 (v5.3) May 17, 2010
D Q
(BMUX)
(BQ)
(Optional)
UG190_5_20_050506
Output (Q)
Registered
Output
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