XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 59
XC4010L-5PQ208C
Manufacturer Part Number
XC4010L-5PQ208C
Description
IC 3.3V FPGA 400 CLB'S 208-PQFP
Manufacturer
Xilinx Inc
Series
XC4000r
Datasheet
1.XC4005L-5PC84C.pdf
(175 pages)
Specifications of XC4010L-5PQ208C
Number Of Logic Elements/cells
950
Number Of Labs/clbs
400
Total Ram Bits
12800
Number Of I /o
160
Number Of Gates
10000
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
208-BFQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
122-1124
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 59 of 175
- Download datasheet (2Mb)
Note that DONE is an open-drain output and does not go
High unless an internal pull-up is activated or an external
pull-up is attached. The internal pull-up is activated as the
default by MakeBits, the bitstream generation software.
Release of User I/O After DONE Goes High
By default, the user I/O are released one CCLK cycle after
the DONE pin goes High. If CCLK is not clocked after
DONE goes High, the outputs remain in their initial state —
3-stated, with a 50 k
DONE High to active user I/O is controlled by a MakeBits
option.
September 18, 1996 (Version 1.04)
Figure 50: Start-up Logic
CLEAR MEMORY
LENGTH COUNT
STARTUP
STARTUP.CLK
USER NET
CCLK
FULL
Q3
Q2
*
*
*
S
K
- 100 k
Q
Q0
0
1
M
*
1
0
*
1
0
0
1
CONFIGURATION BIT OPTIONS SELECTED BY USER IN "MAKEBITS"
Q1/Q4
DONE
IN
pull-up. The delay from
D
K
GSR ENABLE
GSR INVERT
STARTUP.GSR
STARTUP.GTS
GTS INVERT
GTS ENABLE
Q
Q1
D
K
CONTROLLED BY STARTUP SYMBOL
IN THE USER SCHEMATIC (SEE
LIBRARIES GUIDE)
Q
Q2
1
0
M
*
Release of Global Set/Reset After DONE Goes
High
By default, Global Set/Reset (GSR) is released two CCLK
cycles after the DONE pin goes High. If CCLK is not
clocked twice after DONE goes High, all flip-flops are held
in their initial set or reset state. The delay from DONE High
to GSR inactive is controlled by a MakeBits option.
Configuration Complete After DONE Goes High
Three full CCLK cycles are required after the DONE pin
goes High, as shown in
not clocked three times after DONE goes High, readback
cannot be initiated and most boundary scan instructions
cannot be used.
D
Q
K
S
R
Q
Q3
GLOBAL SET/RESET OF
ALL CLB AND IOB FLIP-FLOP
IOBs OPERATIONAL PER CONFIGURATION
GLOBAL 3-STATE OF ALL IOBs
D
K
Q
Q4
Figure 49 on page
1
0
X1528
" FINISHED "
ENABLES BOUNDARY
SCAN, READBACK AND
CONTROLS THE OSCILLATOR
61. If CCLK is
DONE
4-63
Related parts for XC4010L-5PQ208C
Image
Part Number
Description
Manufacturer
Datasheet
Request
R
Part Number:
Description:
IC 3.3V FPGA 400 CLB'S 84-PLCC
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC LOGIC CL ARRAY 10K GAT 208PQ
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
FPGA XC4000 Family 10K Gates 400 Cells 111MHz CMOS Technology 5V 160-Pin PQFP
Manufacturer:
Xilinx Inc
Part Number:
Description:
IC CPLD .8K 36MCELL 44-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 72MCRCELL 10NS 44VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 1.6K 72MCELL 64-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CR-II CPLD 64MCELL 44-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 1.6K 72MCELL 100-TQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CR-II CPLD 64MCELL 56-BGA
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 72MCRCELL 7.5NS 44VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CR-II CPLD 64MCELL 100-VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 1.6K 72MCELL 100-TQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 72MCRCELL 7.5NS 64VQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 1.6K 72MCELL 100-TQFP
Manufacturer:
Xilinx Inc
Datasheet:
Part Number:
Description:
IC CPLD 1.5K 64MCELL HP 44-VQFP
Manufacturer:
Xilinx Inc