XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 60

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

XC4000 Series Field Programmable Gate Arrays
Configuration Through the Boundary Scan
Pins
XC4000-Series devices can be configured through the
boundary scan pins. The basic procedure is as follows:
• Power up the FPGA with INIT held Low (or drive the
• Issue the CONFIG command to the TMS input
• Wait for INIT to go High
• Sequence the boundary scan Test Access Port to the
• Toggle TCK to clock data into TDI pin.
The user must account for all TCK clock cycles after INIT
goes High, as all of these cycles affect the Length Count
compare.
For more detailed information, refer to the Xilinx application
note XAPP017, “ Boundary Scan in XC4000 Devices .” This
application note also applies to XC4000E and XC4000EX
devices.
4-64
Figure 51: Readback Schematic Example
PROGRAM pin Low for more than 300 ns followed by a
High while holding INIT Low). Holding INIT Low allows
enough time to issue the CONFIG command to the
FPGA. The pin can be used as I/O after configuration if
a resistor is used to hold INIT Low.
SHIFT-DR state
MD0
IF UNCONNECTED,
DEFAULT IS CCLK
READ_TRIGGER
IBUF
TRIG
CLK
READBACK
Readback
The user can read back the content of configuration mem-
ory and the level of certain internal nodes without interfer-
ing with the normal operation of the device.
Readback not only reports the downloaded configuration
bits, but can also include the present state of the device,
represented by the content of all flip-flops and latches in
CLBs and IOBs, as well as the content of function genera-
tors used as RAMs.
Note that in XC4000-Series devices, configuration data is
not inverted with respect to configuration as it is in XC2000
and XC3000 families.
Readback of Express mode bitstreams results in data that
does not resemble the original bitstream, because the bit-
stream format differs from other modes.
XC4000-Series Readback does not use any dedicated
pins, but uses four internal nets (RDBK.TRIG, RDBK.DATA,
RDBK.RIP and RDBK.CLK) that can be routed to any IOB.
To access the internal Readback signals, place the READ-
BACK library symbol and attach the appropriate pad sym-
bols, as shown in
After Readback has been initiated by a Low-to-High transi-
tion on RDBK.TRIG, the RDBK.RIP (Read In Progress)
output goes High on the next rising edge of RDBK.CLK.
Subsequent rising edges of this clock shift out Readback
data on the RDBK.DATA net.
Readback data does not include the preamble, but starts
with five dummy bits (all High) followed by the Start bit
(Low) of the first frame. The first two data bits of the first
frame are always High.
Each frame ends with four error check bits. They are read
back as High. The last seven bits of the last frame are also
read back as High. An additional Start bit (Low) and an
11-bit Cyclic Redundancy Check (CRC) signature follow,
before RDBK.RIP returns Low.
DATA
RIP
OBUF
Figure
READ_DATA
September 18, 1996 (Version 1.04)
51.
X1786
MD1