XC4010L-5PQ208C Xilinx Inc, XC4010L-5PQ208C Datasheet - Page 7

• Manufacturer Part Number: XC4010L-5PQ208C
• Description: IC 3.3V FPGA 400 CLB'S 208-PQFP
• Manufacturer: Xilinx Inc
• Series: XC4000r

Specifications of XC4010L-5PQ208C

• Number Of Logic Elements/cells: 950
• Number Of Labs/clbs: 400
• Total Ram Bits: 12800
• Number Of I /o: 160
• Number Of Gates: 10000
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: 0°C ~ 85°C
• Package / Case: 208-BFQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 122-1124

Detailed Functional Description
XC4000-Series devices achieve high speed through
advanced semiconductor technology and improved archi-
tecture. The XC4000E and XC4000EX support system
clock rates of up to 66 MHz and internal performance in
excess of 150 MHz. Compared to older Xilinx FPGA fami-
lies, XC4000-Series devices are more powerful. They offer
on-chip edge-triggered and dual-port RAM, clock enables
on I/O flip-flops, and wide-input decoders. They are more
versatile in many applications, especially those involving
RAM. Design cycles are faster due to a combination of
increased routing resources and more sophisticated soft-
ware.
Basic Building Blocks
Xilinx user-programmable gate arrays include two major
configurable elements: configurable logic blocks (CLBs)
and input/output blocks (IOBs).
• CLBs provide the functional elements for constructing
• IOBs provide the interface between the package pins
Three other types of circuits are also available:
• 3-State buffers (TBUFs) driving horizontal longlines are
• Wide edge decoders are available around the periphery
• An on-chip oscillator is provided.
Programmable interconnect resources provide routing
paths to connect the inputs and outputs of these config-
urable elements to the appropriate networks.
The functionality of each circuit block is customized during
configuration by programming internal static memory cells.
The values stored in these memory cells determine the
logic functions and interconnections implemented in the
FPGA.
Each of these available circuits is described in this section.
Configurable Logic Blocks (CLBs)
Configurable Logic Blocks implement most of the logic in
an FPGA. The principal CLB elements are shown in
Figure
selected soft macros is shown in
Two 4-input function generators (F and G) offer unrestricted
versatility. Most combinatorial logic functions need four or
fewer inputs. However, a third function generator (H) is pro-
vided. The H function generator has three inputs. Either
1. When three separate functions are generated, one of the function outputs must be captured in a flip-flop internal to the CLB. Only two
September 18, 1996 (Version 1.04)
unregistered function generator outputs are available from the CLB.
the user’s logic.
and internal signal lines.
associated with each CLB.
of each device.
1.
The number of CLBs needed to implement
Table
3.
zero, one, or both of these inputs can be the outputs of F
and G; the other input(s) are from outside the CLB. The
CLB can, therefore, implement certain functions of up to
nine variables, like parity check or expandable-identity
comparison of two sets of four inputs.
Each CLB contains two storage elements that can be used
to store the function generator outputs. However, the stor-
age elements and function generators can also be used
independently. These storage elements can be configured
as flip-flops in both XC4000E and XC4000EX devices; in
the XC4000EX they can optionally be configured as
latches. DIN can be used as a direct input to either of the
two storage elements. H1 can drive the other through the H
function generator. Function generator outputs can also
drive two outputs independent of the storage element out-
puts. This versatility increases logic capacity and simplifies
routing.
Thirteen CLB inputs and four CLB outputs provide access
to the function generators and storage elements. These
inputs and outputs connect to the programmable intercon-
nect resources outside the block.
Function Generators
Four independent inputs are provided to each of two func-
tion generators (F1 - F4 and G1 - G4). These function gen-
erators, with outputs labeled F’ and G’, are each capable of
implementing any arbitrarily defined Boolean function of
four inputs. The function generators are implemented as
memory look-up tables. The propagation delay is therefore
independent of the function implemented.
A third function generator, labeled H’, can implement any
Boolean function of its three inputs. Two of these inputs
can optionally be the F’ and G’ functional generator out-
puts. Alternatively, one or both of these inputs can come
from outside the CLB (H2, H0). The third input must come
from outside the block (H1).
Signals from the function generators can exit the CLB on
two outputs. F’ or H’ can be connected to the X output. G’
or H’ can be connected to the Y output.
A CLB can be used to implement any of the following func-
tions:
• any function of up to four variables, plus any second
• any single function of five variables
• any function of four variables together with some
• some functions of up to nine variables.
function of up to four unrelated variables, plus any third
function of up to three unrelated variables
functions of six variables
1
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