XC5202-6PQ100C Xilinx Inc, XC5202-6PQ100C Datasheet - Page 50
XC5202-6PQ100C
Manufacturer Part Number
XC5202-6PQ100C
Description
IC FPGA 64 CLB'S 100-PQFP
Manufacturer
Xilinx Inc
Series
XC5200r
Datasheet
1.XC5206-5PQ208C.pdf
(73 pages)
Specifications of XC5202-6PQ100C
Number Of Logic Elements/cells
256
Number Of Labs/clbs
64
Number Of I /o
81
Number Of Gates
3000
Voltage - Supply
4.75 V ~ 5.25 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 85°C
Package / Case
100-BQFP
Case
QFP100
Dc
99+
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Total Ram Bits
-
Other names
122-1132
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
XC5202-6PQ100C
Manufacturer:
XILINX
Quantity:
182
Company:
Part Number:
XC5202-6PQ100C
Manufacturer:
XILINX
Quantity:
5 530
Company:
Part Number:
XC5202-6PQ100C
Manufacturer:
XILINX
Quantity:
5 510
Company:
Part Number:
XC5202-6PQ100C
Manufacturer:
XILINX
Quantity:
875
Part Number:
XC5202-6PQ100C
Manufacturer:
XILINX/赛灵思
Quantity:
20 000
XC5200 Series Field Programmable Gate Arrays
XC5200 Boundary Scan (JTAG) Switching Characteristic Guidelines
The following guidelines reflect worst-case values over the recommended operating conditions. They are expressed in units
of nanoseconds and apply to all XC5200 devices unless otherwise noted.
7-132
Setup and Hold
Input (TDI) to clock (TCK)
Input (TDI) to clock (TCK)
Input (TMS) to clock (TCK)
Input (TMS) to clock (TCK)
Propagation Delay
Clock (TCK) to Pad (TDO)
Clock
Clock (TCK) High
Clock (TCK) Low
F
Note 1:
MAX
setup time
hold time
setup time
hold time
(MHz)
Input pad setup and hold times are specified with respect to the internal clock.
Description
Product Obsolete or Under Obsolescence
Speed Grade
T
T
Symbol
T
T
T
T
TMSTCK
TCKTMS
T
TDITCK
TCKTDI
F
TCKPO
TCKH
TCKL
MAX
30.0
15.0
30.0
30.0
Min
0
0
-6
Max
30.0
10.0
30.0
15.0
30.0
30.0
Min
0
0
-5
Max
30.0
10.0
November 5, 1998 (Version 5.2)
30.0
15.0
30.0
30.0
Min
0
0
-4
Max
30.0
10.0
30.0
15.0
30.0
30.0
Min
0
0
-3
Max
30.0
10.0
R