AT94K10AL-25AQC Atmel, AT94K10AL-25AQC Datasheet - Page 51
AT94K10AL-25AQC
Manufacturer Part Number
AT94K10AL-25AQC
Description
IC FPSLIC 10K GATE 25MHZ 100TQFP
Manufacturer
Atmel
Series
FPSLIC®r
Specifications of AT94K10AL-25AQC
Core Type
8-bit AVR
Speed
25MHz
Interface
I²C, UART
Program Sram Bytes
20K-32K
Fpga Sram
4kb
Data Sram Bytes
4K ~ 16K
Fpga Core Cells
576
Fpga Gates
10K
Fpga Registers
846
Voltage - Supply
3 V ~ 3.6 V
Mounting Type
Surface Mount
Operating Temperature
0°C ~ 70°C
Package / Case
100-TQFP, 100-VQFP
For Use With
ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
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1138I–FPSLI–1/08
Status Register – SREG
The AVR status register
Note:
• Bit 7 - I: Global Interrupt Enable
The global interrupt enable bit must be set (one) for the interrupts to be enabled. The individual
interrupt enable control is then performed in separate control registers. If the global interrupt
enable register is cleared (zero), none of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit is cleared by the hardware after an interrupt has occurred,
and is set by the RETI instruction to enable subsequent interrupts.
• Bit 6 - T: Bit Copy Storage
The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source and desti-
nation for the operated bit. A bit from a register in the register file can be copied into T by the
BST instruction, and a bit in T can be copied into a bit in a register in the register file by the BLD
instruction.
• Bit 5 - H: Half-carry Flag
The half-carry flag H indicates a half-carry in some arithmetic operations.
• Bit 4 - S: Sign Bit, S = N ⊕ V
The S-bit is always an exclusive or between the negative flag N and the two’s complement over-
flow flag V.
• Bit 3 - V: Two’s Complement Overflow Flag
The two’s complement overflow flag V supports two’s complement arithmetics.
• Bit 2 - N: Negative Flag
The negative flag N indicates a negative result from an arithmetical or logical operation.
• Bit 1 - Z: Zero Flag
The zero flag Z indicates a zero result from an arithmetical or logical operation.
• Bit 0 - C: Carry Flag
The carry flag C indicates a carry in an arithmetical or logical operation.
BitM
$3F ($5F)
Read/Write
Initial Value
1. Note that the status register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt routine. This must be handled by software.
7
I
R/W
0
(1)
6
T
R/W
0
– SREG – at I/O space location $3F ($5F) is defined as:
5
H
R/W
0
4
S
R/W
0
AT94KAL Series FPSLIC
3
V
R/W
0
2
N
R/W
0
1
Z
R/W
0
0
C
R/W
0
SREG
51
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