AT94K40AL-25DQU Atmel, AT94K40AL-25DQU Datasheet - Page 76

• Manufacturer Part Number: AT94K40AL-25DQU
• Description: IC FPSLIC 40K GATE 25MHZ 208PQFP
• Manufacturer: Atmel
• Series: FPSLIC®r

Specifications of AT94K40AL-25DQU

• Core Type: 8-bit AVR
• Speed: 18MHz
• Interface: I²C, UART
• Program Sram Bytes: 20K-32K
• Fpga Sram: 18kb
• Data Sram Bytes: 4K ~ 16K
• Fpga Core Cells: 2304
• Fpga Gates: 40K
• Fpga Registers: 2862
• Voltage - Supply: 3 V ~ 3.6 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 208-MQFP, 208-PQFP
• For Use With: ATSTK594 - BOARD FPSLIC DAUGHTER FOR STK500
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

4.18.6
4.19
4.19.1
4.19.2
76
IEEE 1149.1 (JTAG) Boundary-scan
AT94KAL Series FPSLIC
On-chip Debug Specific JTAG Instructions
Features
System Overview
The On-Chip debug support is considered being private JTAG instructions, and distributed
within ATMEL and to selected third-party vendors only.
Table 4-8.
•
•
•
•
•
The Boundary-Scan chain has the capability of driving and observing the logic levels on the
AVR’s digital I/O pins. At system level, all ICs having JTAG capabilities are connected serially by
the TDI/TDO signals to form a long shift register. An external controller sets up the devices to
drive values at their output pins, and observe the input values received from other devices. The
controller compares the received data with the expected result. In this way, Boundary-Scan pro-
vides a mechanism for testing interconnections and integrity of components on Printed Circuits
Boards by using the 4 TAP signals only.
The four IEEE 1149.1 defined mandatory JTAG instructions IDCODE, BYPASS, SAMPLE/PRE-
LOAD, and EXTEST, as well as the AVR specific public JTAG instruction AVR_RESET can be
used for testing the Printed Circuit Board. Initial scanning of the data register path will show the
JTAG Instruction
EXTEST
IDCODE
SAMPLE_PRELOAD
RESERVED
PRIVATE
PRIVATE
PRIVATE
RESERVED
PRIVATE
PRIVATE
PRIVATE
PRIVATE
AVR_RESET
RESERVED
RESERVED
BYPASS
JTAG (IEEE std. 1149.1 compliant) Interface
Boundary-scan Capabilities According to the JTAG Standard
Full Scan of All Port Functions
Supports the Optional IDCODE Instruction
Additional Public AVR_RESET Instruction to Reset the AVR
JTAG Instruction and Code
4-bit Code
$A (1010)
$B (1011)
$C (1100)
$D (1101)
$E (1110)
$0 (0000)
$1 (0001)
$2 (0010)
$3 (0011)
$4 (0100)
$5 (0101)
$6 (0110)
$7 (0111)
$8 (1000)
$9 (1001)
$F (1111)
Selected Scan Chain
AVR I/O Boundary
Device ID
AVR I/O Boundary
N/A
FPSLIC On-chip Debug System
FPSLIC On-chip Debug System
FPSLIC On-chip Debug System
N/A
FPSLIC On-chip Debug System
FPSLIC On-chip Debug System
FPSLIC On-chip Debug System
FPSLIC On-chip Debug System
AVR Reset
N/A
N/A
Bypass
Table 4-8
lists the instruction opcode.
# Bits
1138I–FPSLI–1/08
69
32
69
–
–
–
–
–
–
–
–
–
1
–
–
1