20-101-0732 Rabbit Semiconductor, 20-101-0732 Datasheet - Page 28
20-101-0732
Manufacturer Part Number
20-101-0732
Description
INTERFACE SMART SCREEN OP7100
Manufacturer
Rabbit Semiconductor
Datasheet
1.101-0303.pdf
(126 pages)
Specifications of 20-101-0732
Module/board Type
Single Board Computer Module
For Use With/related Products
OP7100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
20-101-732
20-101-732
20-101-732
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watchdog timer is
hitwd
A program can read the state of the
makes it possible to determine whether a watchdog timeout occurred. The
following sample program shows how to do this when a program starts or
restarts.
Power Shutdown and Reset
When VCC (+5 V) drops below V
ADM691 supervisor asserts
V
devices to power up and stabilize before the CPU starts.
PFI “Early Warning”
When
the supervisor asserts
program to clean up and get ready for shutdown. The underlying assump-
tion here is that
the ADM691 asserts
In order to improve the performance of the power-failure interrupt circuit,
we have added some hysteresis to the power-failure comparator by adding
a resistor, R34, between the comparator input and output pins. R34 can be
found on the 175-0196 and the 175-0211 versions of the OP7100. The
hysteresis prevents the comparator from switching rapidly—and therefore
generating multiple interrupts—when the input voltage is falling slowly.
Once the comparator switches (DC IN falls to approximately 8.5 V), this
feedback holds the input (PFI) low and prevents further interrupts from
being generated. At this point, the 5 V regulator still has sufficient voltage to
keep the processor operating, so that an interrupt service routine can
perform shutdown tasks and “tidying up” before the Vcc line fails. The
comparator will not turn the output (PFO) high until DC IN has risen to
about 9.2 V. The hysteresis will also help prevent any system oscillation in
adverse power supply/loading situations.
The voltage at which the power-failure interrupt occurs may be changed by
adjusting the values of R29 and R30, which are shown in Figure 3-3. To
calculate the values of these components, let V
PFO turns off as DC IN falls, and let V
on as DC IN rises.
28 Hardware
MIN
and stays that way for at least 50 ms. This delay allows the system’s
PFI
in a routine that runs periodically at the lowest software priority level.
main(){
}
if( wderror() ) wd _ cleanup();
hitwd();
...
drops below 1.3 V ± 0.05 V (i.e., DCIN drops below ~10 V),
PFI
hitwd
will cause the interrupt during a power failure before
/RESET
/NMI
. To hold the watchdog timer at bay, make a call to
(nonmaskable interrupt), and allows the
/RESET
.
MIN
WDO
and holds it until VCC goes above
(between 4.5 V and 4.75 V), the
H
be the voltage at which PFO turns
line with a call to
L
be the voltage at which
wderror
OP7100
. This
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