20-101-0732 Rabbit Semiconductor, 20-101-0732 Datasheet - Page 45
20-101-0732
Manufacturer Part Number
20-101-0732
Description
INTERFACE SMART SCREEN OP7100
Manufacturer
Rabbit Semiconductor
Datasheet
1.101-0303.pdf
(126 pages)
Specifications of 20-101-0732
Module/board Type
Single Board Computer Module
For Use With/related Products
OP7100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
20-101-732
20-101-732
20-101-732
- Current page: 45 of 126
- Download datasheet (780Kb)
Asynchronous Serial Communication Interface
The Z180 incorporates an asynchronous serial communication interface
(ACSI) that supports two independent full-duplex channels.
ASCI Status Registers
A status register for each channel provides information about the state of
each channel and allows interrupts to be enabled and disabled.
/DCD0 (Data Carrier Detect)
This bit echoes the state of the
when the input to the pin switches from high to low, the data bit switches
low only after STAT0 has been read. The receiver is held to reset as long
as the input pin is held high. This function is not generally useful because
an interrupt is requested as long as
mer to disable the receiver interrupts to avoid endless interrupts. A better
design would cause an interrupt only when the state of the pin changes.
This pin is tied to ground in the CM7000.
TIE (Transmitter Interrupt Enable)
This bit masks the transmitter interrupt. If set to 1, an interrupt is requested
whenever TDRE is 1. The interrupt is not edge-triggered. Set this bit to 0
to stop sending. Otherwise, interrupts will be requested continuously as
soon as the transmitter data register is empty.
TDRE (Transmitter Data Register Empty)
A 1 means that the channel is ready to accept another character. A high
level on the
ready.
OP7100
STAT0
STAT1
RDRF
RDRF
R
R
7
7
/CTS
(04H)
(05H)
OVRN
OVRN
pin forces this bit to 0 even though the transmitter is
R
R
6
6
PE
PE
R
R
5
5
/DCD0
FE
FE
R
R
4
4
/DCD0
input pin for Channel 0. However,
R / W
R / W
RIE
RIE
is a 1. This forces the program-
3
3
CTS1E
/DCD0
R
R
2
2
TDRE
TDRE
R
R
1
1
Hardware 45
R / W
TIE
R / W
TIE
0
0
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