CY8C20336-24LQXI Cypress Semiconductor Corp, CY8C20336-24LQXI Datasheet - Page 29
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CY8C20336-24LQXI
Manufacturer Part Number
CY8C20336-24LQXI
Description
IC CAPSENSE 20 I/O 8K 24UQFN
Manufacturer
Cypress Semiconductor Corp
Series
CapSense® Controllersr
Datasheet
1.CY8C20236-24LKXI.pdf
(39 pages)
Specifications of CY8C20336-24LQXI
Applications
Capacitive Sensing
Core Processor
M8C
Program Memory Type
FLASH (8 kB)
Controller Series
CY8C20xx6
Ram Size
1K x 8
Interface
I²C, SPI
Number Of I /o
20
Voltage - Supply
1.71 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
24-UQFN Exposed Pad, 24-HUQFN
Operating Temperature (min)
-40C
Operating Temperature (max)
85C
Technology
CMOS
Processing Unit
Microprocessor
Operating Supply Voltage (min)
1.71V
Operating Supply Voltage (typ)
1.8/2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Package Type
QFN EP
Screening Level
Industrial
Pin Count
24
Mounting
Surface Mount
Rad Hardened
No
Processor Series
CY8C20x36
Core
M8C
Data Bus Width
8 bit
Mounting Style
SMD/SMT
Development Tools By Supplier
CY3280-20X66
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1000 - ISP 4PORT FOR CYPRESS PSOC MCU
Lead Free Status / Rohs Status
Details
Other names
428-2942
AC I2C Specifications
The following table lists guaranteed maximum and minimum specifications for the entire voltage and temperature ranges.
Table 33. AC Characteristics of the I2C SDA and SCL Pins
Document Number: 001-12696 Rev. *E
F
T
T
T
T
T
T
T
T
T
Note
11. A Fast-Mode I2C-bus device can be used in a Standard Mode I2C-bus system, but the requirement t
SCLI2C
HDSTAI2C
LOWI2C
HIGHI2C
SUSTAI2C
HDDATI2C
SUDATI2C
SUSTOI2C
BUFI2C
SPI2C
Symbol
SDA
SCL
if the device does not stretch the LOW period of the SCL signal. If such device does stretch the LOW period of the SCL signal, it must output the next data bit to the
SDA line t
rmax
SCL Clock Frequency
Hold Time (repeated) START Condition. After this period, the first clock pulse is
generated.
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Setup Time for a Repeated START Condition
Data Hold Time
Data Setup Time
Setup Time for STOP Condition
Bus Free Time Between a STOP and START Condition
Pulse Width of spikes are suppressed by the input filter.
S
+ t
T
HDSTAI2C
SU;DAT
T
LOWI2C
= 1000 + 250 = 1250 ns (according to the Standard-Mode I2C-bus specification) before the SCL line is released.
T
Figure 14. Definition for Timing for Fast/Standard Mode on the I
HDDATI2C
T
T
HIGHI2C
SUDATI2C
Description
T
SUSTAI2C
Sr
T
HDSTAI2C
SU;DAT
≥ 250 ns must then be met. This automatically be the case
T
SUSTOI2C
T
SPI2C
Min
250
4.0
4.7
4.0
4.7
4.0
4.7
0
0
–
Standard
2
CY8C20X36/46/66/96
C Bus
Mode
Max
100
P
–
–
–
–
–
–
–
–
–
T
BUFI2C
100
Fast Mode
Min
0.6
1.3
0.6
0.6
0.6
1.3
0
0
0
[11]
S
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Max
400
50
–
–
–
–
–
–
–
–
Units
kHz
μs
μs
μs
μs
μs
μs
μs
ns
ns
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