XE8807AMI026TLF Semtech, XE8807AMI026TLF Datasheet - Page 120

• Manufacturer Part Number: XE8807AMI026TLF
• Description: IC MCU LOW PWR MTP FLASH 32-TQFP
• Manufacturer: Semtech

Specifications of XE8807AMI026TLF

• Applications: Sensing Machine
• Core Processor: RISC
• Program Memory Type: FLASH (11 kB)
• Controller Series: XE8000
• Ram Size: 512 x 8
• Interface: UART, USRT
• Number Of I /o: 24
• Voltage - Supply: 2.4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 32-TQFP, 32-VQFP
• For Use With: XE8000MP - PROG BOARD AND PROSTART2 CARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: XE8807AMI026TR

16.7 Interrupts or polling
In receive mode, there are two possibilities to detect condition 1 or 2: the detection of the condition can generate
an interrupt or the registers can be polled (reading and checking the RegUsrtCond1 and RegUsrtCond2 registers
for the status of USRT communication).
16.8 Function description
The bit UsrtEnable in RegUsrtCtrl is used to enable the USRT interface and controls the PB[4] and PB[5] pins.
This bit puts these two port B lines in the open drain configuration requested to use the USRT interface.
If no external pull-ups are added on PB[4] and PB[5], the user can activate internal pull-ups by setting PBPullup[4]
and PBPullup[5] in RegPBPullup.
The bits UsrtEnWaitS0, UsrtEnWaitCond1, UsrtWaitS0 in RegUsrtCtrl are used for transmitter/receiver control
of USRT interface.
Figure 16-3 shows the unconditional clock stretching function which is enabled by setting UsrtEnWaitS0.
When UsrtEnWaitS0 is 1, the S0 line will be maintained at 0 after its falling edge (clock stretching). UsrtWaitS0 is
then set to 1, indicating that the S0 line is forced low. One can release S0 by writing to the RegUsrtBufferS1
register.
The same can be done in combination with condition 1 detection by setting the UsrtEnWaitCond1 bit. Figure 16-4
shows the conditional clock stretching function, which is enabled by setting UsrtEnWaitCond1.
© Semtech 2006
S0
UsrtWaitS0
write Reg UsrtBufferS1
Figure 16-3: S0 Stretching (UsrtEnWaitS0=1)
16-5
XE8806A/XE8807A
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