CY7C64713-56LTXC Cypress Semiconductor Corp, CY7C64713-56LTXC Datasheet - Page 9

• Manufacturer Part Number: CY7C64713-56LTXC
• Description: IC MCU USB PHERIPH FX1 56VQFN
• Manufacturer: Cypress Semiconductor Corp
• Series: EZ-USB FX1™r

Specifications of CY7C64713-56LTXC

• Package / Case: 56-VQFN Exposed Pad, 56-HVQFN, 56-SQFN, 56-DHVQFN
• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C647xx
• Ram Size: 16K x 8
• Interface: I²C, USB, USART
• Number Of I /o: 24
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Mounting Style: SMD/SMT
• Operating Temperature Range: 0 C to + 70 C
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 428-1681 - KIT USB FX1 DEVELOPMENT BOARD428-1677 - KIT DEVELOPMENT EZ-USB FX2LP428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 428-2929

Endpoint RAM
Size
■
■
Organization
■
■
■
Setup Data Buffer
A separate 8-byte buffer at 0xE6B8-0xE6BF holds the Setup
data from a CONTROL transfer.
Default Alternate Settings
In the following table, ‘0’ means “not implemented”, and ‘2×’
means “double buffered”.
Document #: 38-08039 Rev. *F
3 × 64 bytes
8 × 512 bytes
EP0—Bidirectional endpoint zero, 64 byte buffer
EP1IN, EP1OUT—64 byte buffers, bulk or interrupt
EP2, 4, 6, 8—Eight 512-byte buffers, bulk, interrupt, or
isochronous, of which only the transfer size is available.
EP4 and EP8 are double buffered, while EP2 and 6 are either
double, triple, or quad buffered. Regardless of the physical size
of the buffer, each endpoint buffer accommodates only one full
speed packet. For bulk endpoints, the maximum number of
bytes it can accommodate is 64, even though the physical
buffer size is 512 or 1024. For an ISOCHRONOUS endpoint
the maximum number of bytes it can accommodate is 1023.
For endpoint configuration options, see
EP0 IN&OUT
(Endpoints 0 and 1)
(Endpoints 2, 4, 6, 8)
EP1 OUT
EP1 IN
EP8
EP2
EP4
EP6
64
64
64
64
64
64
64
64
1
64
64
64
EP4
EP6
EP2
64
64
64
64
64
64
64
64
64
64
64
2
EP2
EP4
EP6
1023
1023
64
Figure
64
64
64
64
64
64
3
Figure 6. Endpoint Configuration
6.
EP2
EP6
EP8
64
64
64
64
64
64
64
64
64
64
64
4
EP2
EP6
64
64
64
64
64
64
64
64
64
64
64
5
EP2
EP6
1023
1023
64
64
64
64
64
64
64
6
Table 6. Default Alternate Settings
External FIFO Interface
Architecture
The FX1 slave FIFO architecture has eight 512-byte blocks in the
endpoint RAM that directly serve as FIFO memories, and are
controlled by FIFO control signals (such as IFCLK, SLCS#,
SLRD, SLWR, SLOE, PKTEND, and flags). The usable size of
these buffers depend on the USB transfer mode as described in
the section
In operation, some of the eight RAM blocks fill or empty from the
SIE, while the others are connected to the I/O transfer logic. The
transfer logic takes two forms: the GPIF for internally generated
control signals or the slave FIFO interface for externally
controlled transfers.
ep0
ep1out
ep1in
ep2
ep4
ep6
ep8
Alternate
Setting
EP2
EP8
1023
EP6
1023
64
64
64
64
64
64
64
7
Organization
64 64
0
0
0
0
0
0
0
EP2
1023
1023
EP6
64
64
64
64
64
64
64
8
64 bulk
64 bulk
64 bulk out (2×) 64 int out (2×) 64 iso out (2×)
64 bulk out (2×) 64 bulk out (2×) 64 bulk out (2×)
64 bulk in (2×) 64 int in (2×)
64 bulk in (2×) 64 bulk in (2×) 64 bulk in (2×)
EP2
EP6
1023
1023
1023
1023
64
64
64
9
1
on page 9.
EP2
EP6
EP8
64
64
64
64
64
64
64
64
64
64
64
10
64
64 int
64 int
EP2 EP2
1023
EP8
1023
1023
1023
64
64
64
64
64
11
2
1023
1023
1023
1023
CY7C64713
12
64
64
64
64 int
64 iso in (2×)
64
64 int
Page 9 of 55
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