CY7C68013A-56PVXC Cypress Semiconductor Corp, CY7C68013A-56PVXC Datasheet - Page 15
![IC MCU USB PERIPH HI SPD 56SSOP](/photos/6/50/65056/428-56-ssop_sml.jpg)
CY7C68013A-56PVXC
Manufacturer Part Number
CY7C68013A-56PVXC
Description
IC MCU USB PERIPH HI SPD 56SSOP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68013A-56PVXC
Package / Case
56-SSOP
Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 105 C
Supply Current
50 mA
Operating Supply Voltage
3 V to 3.6 V
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
24
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, USART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1627
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68013A-56PVXC
Manufacturer:
AD
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1 200
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CY
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Company:
Part Number:
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Manufacturer:
CYPRESS
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20 000
Company:
Part Number:
CY7C68013A-56PVXCES
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CY
Quantity:
5
Document #: 38-08032 Rev. *M
XTALIN
XTALOUT
RESET#
WAKEUP#
SCL
SDA
**PE0
**PE1
IFCLK
CLKOUT
DPLUS
DMINUS
BKPT
PORTC7/GPIFADR7
PORTC6/GPIFADR6
PORTC5/GPIFADR5
PORTC4/GPIFADR4
PORTC3/GPIFADR3
PORTC2/GPIFADR2
PORTC1/GPIFADR1
PORTC0/GPIFADR0
PE7/GPIFADR8
PE6/T2EX
PE5/INT6
PE4/RxD1OUT
PE3/RxD0OUT
PE2/T2OUT
PE1/T1OUT
PE0/T0OUT
D7
D6
D5
D4
D3
D2
D1
D0
EA
**PE0 replaces IFCLK
on CY7C68015A/16A
& PE1 replaces CLKOUT
Port
100
56
128
Figure 6. Signal
INT0#/PA0
INT1#/PA1
WU2/PA3
PSEN#
INT5#
RxD0
RxD1
TxD0
TxD1
INT4
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
WR#
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PA2
PA4
PA5
PA6
PA7
RD#
CS#
OE#
A15
A14
A13
A12
A11
A10
T2
T1
T0
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
GPIF Master
RDY0
RDY1
CTL0
CTL1
CTL2
INT0#/PA0
INT1#/PA1
PA2
WU2/PA3
PA4
PA5
PA6
PA7
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
CTL3
CTL4
CTL5
RDY2
RDY3
RDY4
RDY5
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Slave FIFO
FD[15]
FD[14]
FD[13]
FD[12]
FD[11]
FD[10]
FD[9]
FD[8]
FD[7]
FD[6]
FD[5]
FD[4]
FD[3]
FD[2]
FD[1]
FD[0]
SLRD
SLWR
FLAGA
FLAGB
FLAGC
INT0#/ PA0
INT1#/ PA1
SLOE
WU2/PA3
FIFOADR0
FIFOADR1
PKTEND
PA7/FLAGD/SLCS#
Page 15 of 62
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