CY7C68013A-56PVXC Cypress Semiconductor Corp, CY7C68013A-56PVXC Datasheet - Page 39
![IC MCU USB PERIPH HI SPD 56SSOP](/photos/6/50/65056/428-56-ssop_sml.jpg)
CY7C68013A-56PVXC
Manufacturer Part Number
CY7C68013A-56PVXC
Description
IC MCU USB PERIPH HI SPD 56SSOP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68013A-56PVXC
Package / Case
56-SSOP
Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 105 C
Supply Current
50 mA
Operating Supply Voltage
3 V to 3.6 V
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
24
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, USART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1627
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10.3 Data Memory Read
Table 16. Data Memory Read Parameters
Document #: 38-08032 Rev. *M
t
t
t
t
t
t
t
t
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either
RD# or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for
which is based on the stretch value
Note
CL
AV
STBL
STBH
SCSL
SOEL
DSU
DH
19. t
Parameter
t
t
t
t
ACC2
ACC2
ACC2
ACC3
ACC3
(24 MHz) = 3*t
(48 MHz) = 3*t
(24 MHz) = 5*t
(48 MHz) = 5*t
and t
CLKOUT
CLKOUT
ACC3
are computed from the above parameters as follows:
1/CLKOUT Frequency
Delay from Clock to Valid Address
Clock to RD LOW
Clock to RD HIGH
Clock to CS LOW
Clock to OE LOW
Data Setup to Clock
Data Hold Time
A[15..0]
A[15..0]
[17]
[17]
D[7..0]
D[7..0]
CL
CL
CL
CL
OE#
RD#
RD#
CS#
CS#
– t
– t
– t
– t
AV
AV
AV
AV
–t
– t
–t
– t
DSU
DSU
DSU
DSU
= 106 ns
= 190 ns
t
= 43 ns
= 86 ns.
t
AV
AV
t
t
CL
CL
Description
Figure 13. Data Memory Read Timing Diagram
t
STBL
t
t
ACC1
SCSL
t
SOEL
[19]
Stretch = 0
Stretch = 1
t
data in
DSU
t
ACC1
Min
9.6
0
[19]
t
STBH
t
DH
20.83
41.66
83.2
Typ
t
AV
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
t
data in
DSU
Max
10.7
11.1
11
11
13
t
DH
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Page 39 of 62
48 MHz
24 MHz
12 MHz
Notes
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