CY7C68013A-56PVXC Cypress Semiconductor Corp, CY7C68013A-56PVXC Datasheet - Page 40
![IC MCU USB PERIPH HI SPD 56SSOP](/photos/6/50/65056/428-56-ssop_sml.jpg)
CY7C68013A-56PVXC
Manufacturer Part Number
CY7C68013A-56PVXC
Description
IC MCU USB PERIPH HI SPD 56SSOP
Manufacturer
Cypress Semiconductor Corp
Series
EZ-USB FX2LP™r
Specifications of CY7C68013A-56PVXC
Package / Case
56-SSOP
Applications
USB Microcontroller
Core Processor
8051
Program Memory Type
ROMless
Controller Series
CY7C680xx
Ram Size
16K x 8
Interface
I²C, USB, USART
Number Of I /o
24
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Mounting Style
SMD/SMT
Operating Temperature Range
- 40 C to + 105 C
Supply Current
50 mA
Operating Supply Voltage
3 V to 3.6 V
Controller Family/series
(8051) USB
Core Size
8 Bit
No. Of I/o's
24
Program Memory Size
16KB
Cpu Speed
48MHz
No. Of Timers
3
Embedded Interface Type
I2C, USART, USB
Rohs Compliant
Yes
Data Bus Width
8 bit
Data Ram Size
16 KB
Interface Type
I2C, USART, USB
Maximum Clock Frequency
48 MHz
Number Of Programmable I/os
24
Number Of Timers
3
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
CY4611B - KIT USB TO ATA REFERENCE DESIGN428-1677 - KIT DEVELOPMENT EZ-USB FX2LP
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
428-1627
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
CY7C68013A-56PVXC
Manufacturer:
AD
Quantity:
1 200
Company:
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CY7C68013A-56PVXC
Manufacturer:
CY
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CY7C68013A-56PVXC
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20 000
Company:
Part Number:
CY7C68013A-56PVXCES
Manufacturer:
CY
Quantity:
5
10.4 Data Memory Write
Table 17. Data Memory Write Parameters
When using the AUTPOPTR1 or AUTOPTR2 to address external memory, the address of AUTOPTR1 is only active while either RD#
or WR# are active. The address of AUTOPTR2 is active throughout the cycle and meets the above address valid time for which is
based on the stretch value.
Document #: 38-08032 Rev. *M
t
t
t
t
t
t
AV
STBL
STBH
SCSL
ON1
OFF1
CLKOUT
CLKOUT
Parameter
A[15..0]
A[15..0]
D[7..0]
D[7..0]
CS#
WR#
CS#
WR#
t
t
AV
AV
Delay from Clock to Valid Address
Clock to WR Pulse LOW
Clock to WR Pulse HIGH
Clock to CS Pulse LOW
Clock to Data Turn-on
Clock to Data Hold Time
t
t
CL
CL
t
SCSL
t
ON1
t
ON1
t
STBL
Description
Figure 14. Data Memory Write Timing Diagram
data out
Stretch = 1
data out
t
STBH
Min
0
0
0
0
0
t
t
OFF1
AV
CY7C68013A, CY7C68014A
CY7C68015A, CY7C68016A
Max
10.7
13.0
13.1
11.2
11.2
13.1
Unit
ns
ns
ns
ns
ns
ns
Page 40 of 62
t
OFF1
Notes
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