ADE7566ASTZF8 Analog Devices Inc, ADE7566ASTZF8 Datasheet - Page 71

• Manufacturer Part Number: ADE7566ASTZF8
• Description: IC ENERGY METER MCU 8K 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7566ASTZF8

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (8 kB)
• Controller Series: ADE75xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Preliminary Technical Data
Table 54. Program Control SFR (PCON, 0x87)
Bit No.
7
6 to 0
Table 55. Data Pointer Low SFR (DPL, 0x82)
Bits
7 to 0
Table 56. Data Pointer High SFR (DPH, 0x83)
Bits
7 to 0
Table 59. Configuration SFR (CFG, 0xAF)
Bit No.
7
6
5
4
3 to 2
1 to 0
Default
0
Default
0
Mnemonic
Reserved
EXTEN
SCPS
MOD38EN
Reserved
XREN1,
XREN0
Default
0
0
Description
Contain the high byte of the data pointer.
Description
Contain the low byte of the data pointer.
Description
This bit should be left set for proper operation.
Enhanced UART Enable Bit.
EXTEN
0
1
Synchronous Communication Selection Bit.
SCPS
0
1
38 kHz Modulation Enable Bit.
MOD38EN
0
1
XRENx
XREN1 OR XREN0 = 1
XREN1 AND XREN0 = 0
Description
SMOD bit. Double baud rate control.
Reserved. Should be left cleared.
Disables MOVX instruction.
Result
Standard 8052 UART without enhanced error-checking features.
Enhanced UART with enhanced error checking (see the UART Additional Features section).
Result
I
SPI port is selected for control of the shared I
Result
38 kHz modulation is disabled.
38 kHz modulation is enabled on the pins selected by the MOD38[7:0] bits in the
Extended Port Configuration SFR (EPCFG, 0x9F).
Result
Enables MOVX instruction to use 256 bytes of extended RAM.
2
C port is selected for control of the shared I
Rev. PrA | Page 71 of 136
Table 57. Data Pointer Register (DPTR, 0x82 and 0x83)
Bits
15 to 0
Table 58. Stack Pointer SFR (SP, 0x81)
Bits
7 to 0
Default
7
Default
0
Description
Contain the 8 LSBs of the pointer for the stack.
2
2
C/SPI pins and SFRs.
C/SPI pins and SFRs.
Description
Contain two byte address of the data
pointer. DPTR is the combination of DPH
and DPL SFRs.
ADE7566/ADE7569