ADE7166ASTZF16 Analog Devices Inc, ADE7166ASTZF16 Datasheet - Page 10

• Manufacturer Part Number: ADE7166ASTZF16
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF16

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
TIMING SPECIFICATIONS
AC inputs during testing were driven at V
and at 0.45 V for Logic 0. Timing measurements were made at V
minimum for Logic 1 and at V
Figure 3.
For timing purposes, a port pin is no longer floating when a
100 mV change from load voltage occurs. A port pin begins to
Table 5. Clock Input (External Clock Driven XTAL1) Parameter
Parameter
t
t
t
t
t
1/t
1
Table 6. I
Parameter
t
t
t
t
t
t
t
t
t
t
t
1
CK
CKL
CKH
CKR
CKF
BUF
L
H
SHD
DSU
DHD
RSU
PSU
R
F
SUP
The internal PLL locks onto a multiple (512×) of the 32.768 kHz external crystal frequency to provide a stable 4.096 MHz internal clock for the system. The core can
Input filtering on both the SCLK and SDATA inputs suppresses noise spikes of <50 ns.
operate at this frequency or at a binary submultiple defined by the CD bits of the POWCON SFR, Address 0xC5[2:0] (see Table 26).
CORE
1
2
SDATA (I/O)
C-Compatible Interface Timing Parameters (400 kHz)
SCLK (I)
V
t
PSU
SWOUT
Description
XTAL1 period
XTAL1 width low
XTAL1 width high
XTAL1 rise time
XTAL1 fall time
Core clock frequency
Description
Bus-free time between stop condition and start condition
SCLK low pulse width
SCLK high pulse width
Start condition hold time
Data setup time
Data hold time
Setup time for repeated start
Stop condition setup time
Rise time of both SCLK and SDATA
Fall time of both SCLK and SDATA
Pulse width of spike suppressed
CONDITION
– 0.5V
0.45V
STOP
PS
IL
t
BUF
maximum for Logic 0, as shown in
CONDITION
START
t
DSU
0.2V
0.2V
SWOUT
TEST POINTS
1
t
SWOUT
SHD
SWOUT
− 0.5 V for Logic 1
MSB
1
– 0.1V
+ 0.9V
Figure 3. Timing Waveform Characteristics
Figure 4. I
t
DHD
2 TO 7
2
Rev. B | Page 10 of 152
C-Compatible Interface Timing
IH
t
L
V
LOAD
Min
LSB
V
V
8
LOAD
LOAD
t
t
SUP
SUP
float when a 100 mV change from the loaded V
occurs, as shown in Figure 3.
C
V
otherwise noted.
LOAD
DD
– 0.1V
+ 0.1V
t
H
= 2.7 V to 3.6 V; all specifications T
t
DSU
for all outputs is equal to 80 pF, unless otherwise noted.
32.768 kHz External Crystal
ACK
REFERENCE
9
POINTS
TIMING
t
RSU
Typ
30.52
6.26
6.26
9
9
1.024
t
DHD
REPEATED
START
S(R)
V
V
LOAD
LOAD
– 0.1V
– 0.1V
Max
Typ
1.3
1.36
1.14
251.35
740
400
12.5
400
200
300
50
t
MIN
F
MSB
t
V
F
LOAD
1
t
to T
R
t
R
MAX
OH
/V
, unless
OL
Unit
μs
μs
μs
ns
ns
MHz
Unit
μs
μs
μs
μs
ns
ns
ns
ns
ns
ns
ns
level