ADE7166ASTZF16 Analog Devices Inc, ADE7166ASTZF16 Datasheet - Page 37

• Manufacturer Part Number: ADE7166ASTZF16
• Description: IC ENERGY METER 1PHASE 64LQFP
• Manufacturer: Analog Devices Inc

Specifications of ADE7166ASTZF16

• Applications: Energy Measurement
• Core Processor: 8052
• Program Memory Type: FLASH (16 kB)
• Controller Series: ADE71xx
• Ram Size: 512 x 8
• Interface: I²C, SPI, UART
• Number Of I /o: 20
• Voltage - Supply: 3.135 V ~ 3.465 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Ic Function: Single Phase Energy Measurement IC
• Supply Voltage Range: 3.13V To 3.46V, 2.4V To 3.7V
• Operating Temperature Range: -40°C To +85°C
• Digital Ic Case Style: LQFP
• No. Of Pins: 64
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

OPERATING MODES
PSM0 (NORMAL MODE)
In PSM0, or normal operating mode, V
V
by V
default clock frequency, f
power-on reset or software reset, is 1.024 MHz.
PSM1 (BATTERY MODE)
In PSM1, or battery mode, V
operating mode, the 8052 core and all of the digital circuitry are
enabled by default. The analog circuitry for the ADE energy
metering DSP powered by V
automatically restarts, and the switch to the V
occurs, when the V
the MODE1 register (Address 0x0B) is cleared (see Table 33). The
default f
software reset, is 1.024 MHz.
PSM2 (SLEEP MODE)
PSM2 is a low power consumption sleep mode for use in battery
operation. In this mode, V
2.5 V digital and analog circuitry powered through V
is disabled, including the MCU core, resulting in the following:
•
Table 28. SFRs Maintained in PSM2 Mode
I/O Configuration
Interrupt pins configuration SFR
(INTPR, Address 0xFF); see Table 17
Peripheral configuration SFR
(PERIPH, Address 0xF4);
see Table 20
Port 0 weak pull-up enable SFR
(PINMAP0, Address 0xB2); see
Table 157
Port 1 weak pull-up enable SFR
(PINMAP1, Address 0xB3); see
Table 158
Port 2 weak pull-up enable SFR
(PINMAP2, Address 0xB4); see
Table 159
Scratch Pad 1 SFR (SCRATCH1,
Address 0xFB); see Table 22
Scratch Pad 2 SFR (SCRATCH2,
Address 0xFC); see Table 23
Scratch Pad 3 SFR (SCRATCH3,
Address 0xFD); see Table 24
Scratch Pad 4 SFR (SCRATCH4,
Address 0xFE); see Table 25
1
This feature is not available in the ADE7116.
DD
. All of the analog circuitry and the digital circuitry powered
INTD
The RAM in the MCU is no longer valid.
CORE
and V
for PSM1, established during a power-on reset or
INTA
are enabled by default. In normal mode, the
DD
supply is >2.75 V and the PWRDN bit in
CORE
SWOUT
SWOUT
INTA
, which is established during a
is connected to V
is disabled. This analog circuitry
is connected to V
Power Supply Management
Battery detection threshold SFR
(BATVTH, Address 0xFA); see
Table 52
Battery switchover configuration
SFR (BATPR, Address 0xF5); see
Table 19
Battery ADC value SFR
(BATADC, Address 0xDF); see
Table 54
Peripheral ADC strobe period SFR
(STRBPER, Address 0xF9);
see Table 49
Temperature and supply delta SFR
(DIFFPROG, Address 0xF3); see
Table 50
V
Address 0xEF); see Table 53
Temperature ADC value SFR
(TEMPADC, Address 0xD7); see
Table 55
DCIN
SWOUT
ADC value SFR (VDCINADC,
DD
is connected to
1
1
1
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
power supply
BAT
1
BAT
INTA
. All of the
. In this
and V
Rev. B | Page 37 of 152
INTD
1
RTC Peripherals
RTC nominal compensation SFR
(RTCCOMP, Address 0xF6); see
Table 134
RTC temperature compensation
SFR (TEMPCAL, Address 0xF7);
see Table 135
RTC configuration SFR (TIMECON,
Address 0xA1); see Table 128
Hundredths of a second counter
SFR (HTHSEC, 0xA2); see Table 129
Seconds counter SFR (SEC, 0xA3);
see Table 130
Minutes counter SFR (MIN, 0xA4);
see Table 131
Hours counter SFR (HOUR, 0xA5);
see Table 132
Alarm interval SFR (INTVAL, 0xA6);
see Table 133
•
The 3.3 V peripherals (temperature ADC
and LCD) are active in PSM2. They can be enabled or disabled
to reduce power consumption and are configured for PSM2
operation when the MCU core is active (see Table 29 for more
information about the peripherals and their PSM2 configuration).
The ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
ADE7569 remain in PSM2 until an event occurs to wake them up.
In PSM2 mode, the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 provide four scratch pad RAM SFRs that
are maintained during this mode. These SFRs can be used
to save data from PSM0 or PSM1 mode when entering PSM2
mode (see Table 22 to Table 25).
In PSM2, the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 maintain some SFRs (see Table 28). The
SFRs that are not listed in this table should be restored when the
part enters PSM0 or PSM1 mode from PSM2 mode.
The program counter for the 8052, also held in volatile
memory, becomes invalid when the 2.5 V supply is shut
down. Therefore, the program does not resume from
where it left off but always starts from the power-on reset
vector when the ADE7116/ADE7156/ADE7166/ADE7169/
ADE7566/ADE7569 exit PSM2.
LCD Peripherals
LCD Segment Enable 2 SFR
(LCDSEGE2, Address 0xED); see
Table 98
LCD Configuration Y SFR
(LCDCONY, Address 0xB1); see
Table 91
LCD Configuration X SFR
(LCDCONX, Address 0x9C); see
Table 89
LCD configuration SFR
(LCDCON, Address 0x95); see
Table 88
LCD clock SFR (LCDCLK,
Address 0x96); see Table 92
LCD segment enable SFR
(LCDSEGE, Address 0x97); see
Table 95
LCD pointer SFR (LCDPTR,
Address 0xAC); see Table 96
LCD data SFR (LCDDAT,
Address 0xAE); see Table 97
1
, V
DCIN
ADC
1
, RTC,