CY7C63413-PVC Cypress Semiconductor Corp, CY7C63413-PVC Datasheet - Page 2

• Manufacturer Part Number: CY7C63413-PVC
• Description: IC MCU 8K USB LS PERIPH 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C63413-PVC

• Applications: USB Microcontroller
• Core Processor: M8B
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C634xx
• Ram Size: 256 x 8
• Interface: PS2, USB
• Number Of I /o: 32
• Voltage - Supply: 4 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 428-1319

1.0 FEATURES ..................................................................................................................................... 5
2.0 FUNCTIONAL OVERVIEW ............................................................................................................. 6
3.0 PIN ASSIGNMENTS ....................................................................................................................... 8
4.0 PROGRAMMING MODEL ............................................................................................................... 8
4.1 14-bit Program Counter (PC) ........................................................................................................... 8
4.2 8-bit Accumulator (A) ....................................................................................................................... 8
4.3 8-bit Index Register (X) .................................................................................................................... 8
4.4 8-bit Program Stack Pointer (PSP) .................................................................................................. 8
4.5 8-bit Data Stack Pointer (DSP) ........................................................................................................ 9
4.6 Address Modes ................................................................................................................................ 9
5.0 INSTRUCTION SET SUMMARY ................................................................................................... 10
6.0 MEMORY ORGANIZATION .......................................................................................................... 11
6.1 Program Memory Organization ...................................................................................................... 11
6.2 Data Memory Organization ............................................................................................................ 12
6.3 I/O Register Summary ................................................................................................................... 13
7.0 CLOCKING .................................................................................................................................... 14
8.0 RESET ...........................................................................................................................................14
8.1 Power-On Reset (POR) ................................................................................................................. 14
8.2 Watch Dog Reset (WDR) ............................................................................................................... 15
9.0 GENERAL PURPOSE I/O PORTS ............................................................................................... 15
9.1 GPIO Interrupt Enable Ports .......................................................................................................... 16
9.2 GPIO Configuration Port ................................................................................................................ 16
10.0 DAC PORT .................................................................................................................................. 17
10.1 DAC Port Interrupts ..................................................................................................................... 18
10.2 DAC Isink Registers ..................................................................................................................... 18
11.0 USB SERIAL INTERFACE ENGINE (SIE) ................................................................................. 18
11.1 USB Enumeration ........................................................................................................................ 19
11.2 PS/2 Operation ............................................................................................................................ 19
11.3 USB Port Status and Control ....................................................................................................... 19
12.0 USB DEVICE ............................................................................................................................... 20
12.1 USB Ports .................................................................................................................................... 20
12.2 Device Endpoints (3) ................................................................................................................... 20
13.0 12-BIT FREE-RUNNING TIMER ................................................................................................. 21
13.1 Timer (LSB) .................................................................................................................................21
13.2 Timer (MSB) ................................................................................................................................ 21
14.0 PROCESSOR STATUS AND CONTROL REGISTER ...............................................................22
4.6.1 Data ........................................................................................................................................................ 9
4.6.2 Direct ...................................................................................................................................................... 9
4.6.3 Indexed ................................................................................................................................................... 9
TABLE OF CONTENTS
2
CY7C63411/12/13
CY7C63511/12/13