PNX1500E/G,557 NXP Semiconductors, PNX1500E/G,557 Datasheet - Page 693

• Manufacturer Part Number: PNX1500E/G,557
• Description: IC MEDIA PROC 240MHZ 456-BGA
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E/G,557

• Applications: Multimedia
• Core Processor: TriMedia
• Controller Series: Nexperia
• Interface: I²C, 2-Wire Serial
• Number Of I /o: 61
• Voltage - Supply: 1.14 V ~ 1.26 V
• Operating Temperature: 0°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 456-BGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Program Memory Type: -
• Ram Size: -
• Lead Free Status / Rohs Status: Compliant
• Other names: 568-1296; 935277746557; PNX1500E/G

Philips Semiconductors
Volume 1 of 1
Table 2: LAN100 Registers
PNX15XX_SER_3
Product data sheet
Bit
1
0
Offset 0x07 2FE8
The Interrupt Clear register is write-only. Writing a 1 to a bit of the register clears the corresponding bit in the Status register.
Writing a 0 to a bit of the register does not affect the corresponding interrupt status.
31:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Offset 0x07 2FEC
The interrupt set register is write-only. Writing a 1 to a bit of the register sets the corresponding bit in the Status register.
Writing a 0 to a bit of the register does not affect the interrupt status.
31:14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Symbol
RxErrorIntEn
RxOverrunIntEn
-
WakeupIntSet
SoftIntSet
TxRtDoneIntSet
TxRtFinishedIntSet
TxRtErrorIntSet
TxRtUnderrunIntSet
TxDoneIntSet
TxFinishedIntSet
TxErrorIntSet
TxUnderrunIntSet
RxDoneIntSet
RxFinishedIntSet
RxErrorIntSet
RxOverrunIntSet
-
WakeupIntSet
SoftIntSet
TxRtDoneIntSet
TxRtFinishedIntSet
TxRtErrorIntSet
TxRtUnderrunIntSet
TxDoneIntSet
TxFinishedIntSet
TxErrorIntSet
TxUnderrunIntSet
RxDoneIntSet
RxFinishedIntSet
RxErrorIntSet
RxOverrunIntSet
Interrupt Clear Register (IntClear)
Interrupt Set Register (IntSet)
…Continued
Acces
s
R/W
R/W
-
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
-
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
WO
Value
Rev. 3 — 17 March 2006
Description
Enable interrupts on receive errors.
Enable interrupts on receive buffer overrun or descriptor underrun
conditions.
Unused
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Writing a 1 clears the corresponding status bit in IntStatus.
Unused
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Writing a 1 sets the corresponding status bit in IntStatus.
Chapter 23: LAN100 — Ethernet Media Access Controller
© Koninklijke Philips Electronics N.V. 2006. All rights reserved.
PNX15xx Series
23-24