PNX1500E NXP Semiconductors, PNX1500E Datasheet
PNX1500E
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PNX1500E Summary of contents
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PNX15xx/952x Series Data Book Volume Connected Media Processor Rev. 4.0 — 03 December 2007 ...
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... NXP Semiconductors Volume PNX15XX_PNX952X_SER_N_4 Product data sheet PNX15xx/952x Series Rev. 4.0 — 03 December 2007 Connected Media Processor © NXP B.V. 2007. All rights reserved. -ii ...
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... NXP Semiconductors Volume Chapter 1: Integrated Circuit Data 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2. Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 2.1 Boundary Scan Notice . . . . . . . . . . . . . . . . . . . . . . 25 2.2 I/O Circuit Summary . . . . . . . . . . . . . . . . . . . . . . . . 25 2.3 Signal Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 2.3.1 Power Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 2.3.2 Pin Reference Voltage . . . . . . . . . . . . . . . . . . . . . . 44 3. Absolute Maximum Ratings 4. PNX15xx/952x Series Operating Conditions 45 4.1 PNX1500 Device ...
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... NXP Semiconductors Volume 10. Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . 101 10.1 GPIO - General Purpose Software I/O and Flexible Serial Interface 101 10.1.1 Software I 101 10.1.2 Timestamping . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 10.1.3 Event sequence monitoring and signal generation 102 10.1.4 GPIO pin reset value . . . . . . . . . . . . . . . . . . . . . . 102 10.2 IR Remote Control Receiver and Blaster Chapter 3: System On Chip Resources 1 ...
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... NXP Semiconductors Volume 2.12.3 Internal PNX15xx/952x Series Clock from Dividers 174 2.12.4 GPIO Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 176 2.12.5 External Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . 177 2.12.6 SPDO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 181 Chapter 6: Boot Module 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 2. Functional Description 2.1 The Boot Modes . . . . . . . . . . . . . . . . . . . . . . . . . . 204 2.2 Boot Module Operation . . . . . . . . . . . . . . . . . . . . 206 2.2.1 MMIO Bus Interface ...
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... NXP Semiconductors Volume 4.11 GPIO Interrupt Registers for the FIFO Queues (One for each FIFO Queue) 4.12 GPIO Module Status Register for all 12 Timestamp Units 304 Chapter 9: DDR Controller 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 313 2. Functional Description 2.1 Start and Warm Start . . . . . . . . . . . . . . . . . . . . . . 314 2.1.1 The Start Mode ...
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... NXP Semiconductors Volume 2.4.7 PLAN (Semi Planar DMA) Unit 2.5 Screen Timing Generator 2.6 Mixer Structure . . . . . . . . . . . . . . . . . . . . . . . . . . . 368 2.6.1 Key Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . 370 2.6.2 Alpha Blending . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 2.7 Output Pipeline Structure 2.7.1 Supported Output Formats 2.7.2 Layer Selection . . . . . . . . . . . . . . . . . . . . . . . . . . . 372 2.7.3 Chrominance Downsampling (CDNS) 2.7.4 Gamma Correction and Noise Shaping (GNSH& ...
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... NXP Semiconductors Volume 3.1 Both Operating Modes . . . . . . . . . . . . . . . . . . . . . 472 3.1.1 Setup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 472 3.1.2 Interrupt Service Routines 3.1.3 Optimized DMA Transfers 3.1.4 Terminating DMA Transfers 3.1.5 Signal Edge Definitions . . . . . . . . . . . . . . . . . . . . 473 3.2 Message Passing Mode . . . . . . . . . . . . . . . . . . . 474 3.3 PNX1300 Series Message Passing Mode Chapter 14: FGPI: Fast General Purpose Interface 1 ...
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... NXP Semiconductors Volume Chapter 16: Audio Input 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 527 2. Functional Description 2.1 Chip Level External Interface 2.2 General Operations . . . . . . . . . . . . . . . . . . . . . . . 530 3. Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 531 3.1 Clock Programming . . . . . . . . . . . . . . . . . . . . . . . 531 3.1.1 Clock System Operation . . . . . . . . . . . . . . . . . . . 531 3.2 Reset-Related Issues . . . . . . . . . . . . . . . . . . . . . 532 3.3 Register Programming Guidelines 3 ...
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... NXP Semiconductors Volume Chapter 19: Memory Based Scaler 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 580 2. Functional Description 2.1 MBS Block Level Diagram 2.2 Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 582 2.2.1 Horizontal Processing Pipeline 2.2.2 Vertical Processing Pipeline 2.3 Data Processing in MBS . . . . . . . . . . . . . . . . . . . 584 2.4 General Operations . . . . . . . . . . . . . . . . . . . . . . . 585 2.4.1 Task Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 585 2 ...
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... NXP Semiconductors Volume 4.0.1 PNX1300 Series versus PNX15xx/952x Series VLD 663 5. Register Descriptions . . . . . . . . . . . . . . . . . . . 663 Chapter 22: Digital Video Disc Descrambler 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 668 1.1 Functional Description . . . . . . . . . . . . . . . . . . . . . 668 Chapter 23: LAN100 — Ethernet Media Access Controller 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 670 2. Functional Description 2.1 Chip I/O and System Interconnections 2 ...
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... NXP Semiconductors Volume Chapter 24: TM3260 Debug 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 747 2. Functional Description 2.1 General Operations . . . . . . . . . . . . . . . . . . . . . . . 747 2.1.1 Test Access Port (TAP 747 2.1.2 TAP Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . 748 2.1.3 PNX15xx/952x Series JTAG Instruction Set 2 Chapter 25 Interface 1. Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 758 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 759 2. Functional Description 2 ...
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... NXP Semiconductors Volume 3.2 Law 2: The “DMA Convention Rule” 4. PNX15xx/952x Series Endian Mode Architecture Details 807 4.1 Global Endian Mode . . . . . . . . . . . . . . . . . . . . . . 807 4.2 Module Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 807 4.3 Module DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 808 4.4 SIMD Programming Issues 4.5 Optional Endian Mode Override 5. Example: Audio In—Programmer’s View 6 ...
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... NXP Semiconductors Volume Chapter 1: Integrated Circuit Data Figure 1: Application Diagram of the Crystal Oscillator 52 Figure 2: SSTL_2 Test Load Condition Figure 3: SSTL_2 Receiver Signal Conditions Figure 4: BPX2T14MCP Test Load Condition Figure 5: BPTS1CHP and BPTS1CP Test Load Condi- tion 55 Figure 6: BPTS3CHP and BPTS3CP Test Load Condi- ...
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... NXP Semiconductors Volume Chapter 6: Boot Module Figure 1: Boot Block Diagram . . . . . . . . . . . . . . . . . . . . 206 Figure 2: System Memory Map and Block Diagram Con- figuration for PNX15xx/952x Series in Standa- lone Mode 212 Chapter 7: PCI-XIO Module Figure 1: PCI-XIO Block Diagram Figure 2: Read Status . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Figure 3: Read Data ...
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... NXP Semiconductors Volume Figure 7: VBI/Programming Data Packet Formats Figure 8: Shadow Mechanism . . . . . . . . . . . . . . . . . . . 379 Figure 9: Shadowing of Registers Figure 10: Resource Layer and ID Chapter 12: Video Input Processor Figure 1: Simplified VIP Block Diagram Figure 2: VIP Module Interface . . . . . . . . . . . . . . . . . . . 430 Figure 3: Digital Video Input Port Timing Relationships in HD Mode ...
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... NXP Semiconductors Volume Chapter 18: SPDIF Input Figure 1: SPDIF Input Block Diagram Figure 2: Serial Format of an IEC60958 Block Figure 3: SPDIF Input: Raw Mode Format Figure 4: SPDIF Input Sample Order View of Memory 560 Figure 5: Endian Mode Byte Address Memory Format 561 Chapter 19: Memory Based Scaler ...
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... NXP Semiconductors Volume Chapter 27: Power Management Chapter 28: Pixel Formats Figure 1: Native Pixel Format Unit Layout Figure 2: Indexed Formats . . . . . . . . . . . . . . . . . . . . . . 791 Figure 3: 16-Bit Pixel-Packed Formats Figure 4: 32-Bit/Pixel Packed Formats Figure 5: UYVY Packed YUV 4:2:2 Format Figure 6: YUY2/2vuy Packed YUV 4:2:2 Format Figure 7: Spatial Sampling Structure of Packed and Pla- ...
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... NXP Semiconductors Volume Chapter 1: Integrated Circuit Data Table 1: PNX1500 I/O Types . . . . . . . . . . . . . . . . . . . . . 26 Table 2: PNX1500 I/O Modes . . . . . . . . . . . . . . . . . . . . 26 Table 3: PNX1500 Special I/Os Table 4: PNX1500 Interface . . . . . . . . . . . . . . . . . . . . . . 28 Table 5: Power Pin List . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Table 6: Pin Reference Voltage Table 7: Absolute Maximum Ratings Table 8: PNX1500 Operating Range and Thermal Characteristics ...
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... NXP Semiconductors Volume Chapter 4: Reset Table 1: RESET Module . . . . . . . . . . . . . . . . . . . . . . . . 149 Chapter 5: The Clock Module Table 1: PNX15xx/952x Series Module and Bus Clocks 154 Table 2: Current Adjustment Values Based on N Table 3: PLL Settings . . . . . . . . . . . . . . . . . . . . . . . . . . 159 Table 4: PLL Characteristics . . . . . . . . . . . . . . . . . . . . 160 Table 5: Internal Clock Dividers Table 6: DDS and PLL Clock Assignment ...
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... NXP Semiconductors Volume Columns 323 Table 5: 1024-Byte Interleaving, 512 Columns Table 6: DDR Timing Parameters Chapter 10: LCD Controller Table 1: LCD Controller Register Summary Chapter 11: QVCP Table 1: Summary of Native Pixel Formats Table 2: Color Key Combining ROPs Table 3: Chroma Key ROP Examples Table 4: ROP Table for Invert/Select/Alpha/KeyPass/ ...
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... NXP Semiconductors Volume Chapter 16: Audio Input Table 1: Audio-In I2S Related Ports Table 2: Sample Rate Settings Table 3: Bit Positions Assigned for Each Data Item Table 4: Example Setup For SAA7366 Table 5: Operating Modes and Memory Formats Table 6: Endian Ordering of Audio Data in Main Memory ...
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... NXP Semiconductors Volume Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder Table 1: Software Reset Procedure Table 2: VLD STATUS . . . . . . . . . . . . . . . . . . . . . . . . . 653 Table 3: VLD Control . . . . . . . . . . . . . . . . . . . . . . . . . . . 654 Table 4: VLD Commands . . . . . . . . . . . . . . . . . . . . . . . 656 Table 5: VLD Command Register Table 6: References for the MPEG-2 Macroblock Chapter 22: Digital Video Disc Descrambler Chapter 23: LAN100 — ...
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... NXP Semiconductors Volume Table 4: Precise Mapping Audio In Sample Time and Bits to Memory Bytes 809 Table 5: DTL Interface Rules . . . . . . . . . . . . . . . . . . . . 811 Table 6: 32 Bit DTL Interface Byte Address Table 7: DTL Interface Rules . . . . . . . . . . . . . . . . . . . . 812 Chapter 30: DCS Network Table 1: DCS Controller_TriMedia Configuration Register Summary 819 ...
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Chapter 1: Integrated Circuit Data PNX15xx/952x Series Data Book – Volume Rev. 4.0 — 03 December 2007 1. Introduction The PNX1500 Media Processor Series is a complete Audio/Video/Graphics system on a chip that contains a high-performance 32-bit ...
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... NXP Semiconductors Volume PNX1500 uses different I/Os depending on the type of the interface, e.g. PCI, or electrical characteristics needed for the functionality, e.g. a clock signal requires sharper edges than a regular signal. The following table summarizes the types of I/ Os, a.k.a. pads, used in PNX1500. Table 1: PNX1500 I/O Types ...
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... NXP Semiconductors Volume • PCI_FRAME_N, PCI_TDRY_N, PCI_IRDY_N, PCI_DEVSEL_N, PCI_STOP_N, PCI_SERR_N, PCI_PERR_N and PCI_INTA_N require an external pull-up. Refer to Section 4.3.3 of PCI 2.2 specification for more details. • Any I/O or I/OD signal of the XIO bus must be pulled-up if they are not used. • ...
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... NXP Semiconductors Volume Remark: The pull-down in the BPT3MCHDT5V pads is NOT strong enough to actually pull down a 5-V TTL input. Instead the TTL input pin sees a ‘1’. Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type System Clock XTAL_IN D11 XTAL_OUT D9 PCI_SYS_CLK ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type MM_CLK M1 MM_CLK_N M2 MM_CS1_N V4 MM_CS0_N L3 MM_RAS_N L1 MM_CAS_N M4 MM_WE_N N3 MM_CKE J2 AVREF N2 MM_BA1 P4 MM_BA0 R4 MM_ADDR12 K4 MM_ADDR11 K3 MM_ADDR10 T4 MM_ADDR09 L4 MM_ADDR08 N4 MM_ADDR07 P1 MM_ADDR06 R1 MM_ADDR05 T1 MM_ADDR04 U3 MM_ADDR03 U4 MM_ADDR02 T3 MM_ADDR01 P3 MM_ADDR00 R2 MM_DQM3 U2 MM_DQM2 V3 MM_DQM1 J4 MM_DQM0 K2 MM_DQS3 ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type MM_DATA31 AD2 MM_DATA30 AD1 MM_DATA29 AB2 MM_DATA28 AC1 MM_DATA27 AB1 MM_DATA26 AA2 MM_DATA25 AA1 MM_DATA24 W2 MM_DATA23 W4 MM_DATA22 Y3 MM_DATA21 Y4 MM_DATA20 AA3 MM_DATA19 AB3 MM_DATA18 AB4 MM_DATA17 AC3 MM_DATA16 AD3 MM_DATA15 ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type PCI_AD31 H24 PCI_AD30 G26 PCI_AD29 J23 PCI_AD28 H25 PCI_AD27 H26 PCI_AD26 K23 PCI_AD25 J25 PCI_AD24 J26 PCI_AD23 L23 PCI_AD22 L24 PCI_AD21 L25 PCI_AD20 L26 PCI_AD19 M24 PCI_AD18 M23 PCI_AD17 ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type PCI_TRDY_N N24 PCI_STOP_N P24 PCI_IDSEL K26 PCI_DEVSEL_N P26 PCI_REQ_N F23 PCI_GNT_N D24 PCI_REQ_A_N G23 PCI_GNT_A_N D25 PCI_REQ_B_N H23 PCI_GNT_B_N D26 PCI_PERR_N P23 PCI_SERR_N R25 PNX15XX_PNX952X_SER_N_4 Product data sheet I/O ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type PCI_INTA_N D23 Additional XIO bus signals to the regular PCI bus signals to implement Flash, IDE drive interface and M68k System Buses. XIO_D15 AA25 XIO_D14 AA26 XIO_D13 AD25 XIO_D12 Y24 XIO_D11 ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDI_D31 AC14 VDI_D30 AF12 VDI_D29 AE12 VDI_D28 AF11 VDI_D27 AC13 VDI_D26 AD11 VDI_D25 AF10 VDI_D24 AE10 VDI_D23 AF9 VDI_D22 AC12 VDI_D21 AD10 VDI_D20 AE9 VDI_D19 AF8 VDI_D18 AD9 VDI_D17 ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDI_CLK2 AC6 VDI_V2 AE1 Video/Data Out Pin Group The video mode provides ITU656 8-, 10- and 16-bit outputs, or digital 24-/30-bit HD YUV outputs, or digital 24-/30-bit RGB/VGA outputs. The data streaming mode provides 8-, 16-bit or 32-bit data streaming output. Refer to Section 7.1 on page 3-125 for a detailed defi ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDO_D31 C26 VDO_D30 E26 VDO_D29 D20 VDO_D28 F24 VDO_D27 F25 VDO_D26 F26 VDO_D25 G24 VDO_D24 G25 VDO_D23 D19 VDO_D22 C25 VDO_D21 B26 VDO_D20 D22 VDO_D19 D21 VDO_D18 C23 VDO_D17 ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDO_CLK2 B19 VDO_AUX E24 FGPO_REC_SYNC C17 FGPO_BUF_SYNC A18 Octal Audio In (audio in always acts as receiver, but can be set as master or slave for A/D timing) AI_OSCLK AF23 AI_SCK AD20 PNX15XX_PNX952X_SER_N_4 Product data sheet ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type AI_WS AD21 AI_SD3 AD22 BPT3MCHDT5V AI_SD2 AC17 BPT3MCHDT5V AI_SD1 AF24 BPT3MCHDT5V AI_SD0 AE23 BPT3MCHDT5V Octal Audio Out (audio out always acts as sender, but can be set as master or slave for D/A timing) ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type AO_WS AE20 AO_SD3 AF21 AO_SD2 AF20 AO_SD1 AE19 AO_SD0 AF19 SPDIF interface SPDI A6 BPT3MCHDT5V SPDO AF22 10/100 LAN interface (MII) LAN_CLK AF18 LAN_TX_CLK/ AF14 LAN_REF_CLK LAN_TX_EN AD13 LAN_TXD3 AF15 ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type LAN_RX_CLK/ AF16 LAN_REF_CLK LAN_RXD3 AD17 LAN_RXD2 AD16 LAN_RXD1 AF17 LAN_RXD0 AE16 LAN_RX_DV AE15 LAN_RX_ER AD15 LAN_MDIO AC26 LAN_MDC AC25 Interface IIC_SDA C8 IIC3M4SDAT5V IIC_SCL D8 GPIO - Multi-function flexible software I/O and universal serial interface Each GPIO pin can be individually set/read by software, or connected to a DMA engine that makes it function as a serial pattern generator or serial observer, so that the software can implement complex bit serial I/O protocols ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type GPIO06/CLOCK06 B9 GPIO05/CLOCK05 A8 GPIO04/CLOCK04 A7 GPIO03/CLOCK03/ A4 BOOT_MODE03 GPIO02/CLOCK02/ A3 BOOT_MODE02 - GPIO01/CLOCK01/ B3 BOOT_MODE01 - GPIO00/CLOCK00/ B4 BOOT_MODE00 - JTAG Interface (debug access port and 1149.1 boundary scan port) JTAG_TDI A1 JTAG_TDO D6 JTAG_TCK B1 JTAG_TMS D5 Power Supplies and Ground Refer to Section 10 ...
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... NXP Semiconductors Volume Table 4: PNX1500 Interface BGA Pad Pin Name Ball Type VDD[] - VSS[] - VSS[] - VSS[] - PNX15XX_PNX952X_SER_N_4 Product data sheet I/O GPIO Type # P Description VDDI PWR - - SoC core power supply. Refer to complete pin list. VSSIS GND - - Ground for the core. Refer to pin list ...
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... NXP Semiconductors Volume 2.3.1 Power Pin List Table 5: Power Pin List Digital Ground 3.3-V VSS VCCP T11 N11 V5 AB7 T12 N12 U5 AB8 T13 N13 T2 AB13 T14 N14 M3 AB14 T15 N15 H3 P22 T16 N16 J5 N22 R11 M11 F4 E13 R12 M12 F5 E14 R13 ...
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... NXP Semiconductors Volume 2.3.2 Pin Reference Voltage Table 6: Pin Reference Voltage 3.3 V Input and/or Output V CCP 5.0 V Input Tolerant 3.3 V Input and/or Output POR_IN_N PCI_AD31 PCI_SYS_CLK RESET_IN_N PCI_AD30 SYS_RST_OUT_N PCI_CLK PCI_AD29 VDO_CLK1 PCI_C/BE03 PCI_AD28 VDO_CLK2 VDO_D33 PCI_C/BE2 PCI_AD27 PCI_C/BE1 PCI_AD26 VDO_D32 ...
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... NXP Semiconductors Volume Table 7: Absolute Maximum Ratings Symbol Description V 3.3 V I/O supply voltage CCP V SSTL DDR-I I/O supply voltage CCM V SoC Core supply voltage DD V Input voltage for 5 V tolerant input pins (i.e. pins supplied by ICCP V ) CCP T Storage temperature range stg ...
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... NXP Semiconductors Volume Table 8: PNX1500 Operating Range and Thermal Characteristics Symbol Description T case Operating case temperature range Top of junction to case thermal resistance (same as JC Top of junction to ambient thermal resistance (still air) JA Table 9: PNX1500 Maximum Operating Speeds 2DDE VLIW CPU MBS TM3260 ...
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... NXP Semiconductors Volume 4.3 PNX1502 Device Table 12: PNX1502 Operating Range and Thermal Characteristics Symbol Description V Global I/O supply voltage CCP V DDR-I I/O supply voltage. DDR400 Operating Mode requires 2.6V 2.47 CCM V Input reference level voltage for the DDR I/Os. REF V SoC Core supply voltage ...
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... NXP Semiconductors Volume Table 15: PNX1520 Maximum Operating Speeds 2DDE VLIW CPU MBS TM3260 DDR-I MMIO VLD (MHz) (MHz) (MHz) (MHz) 266 183 144 115 4.5 PNX9520 Device Qualified in accordance with AEC-Q100 grade 3. Table 16: PNX9520 Operating Range and Thermal Characteristics Symbol Description ...
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... NXP Semiconductors Volume Table 18: PNX9525 Operating Range and Thermal Characteristics Symbol Description T ambient Operating ambient temperature range. Top of junction to case thermal resistance (same as JC Top of junction to ambient thermal resistance (still air) JA Table 19: PNX9525 Maximum Operating Speeds 2DDE VLIW CPU MBS TM3260 ...
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... NXP Semiconductors Volume The standby mode is obtain by specifically turning off the different clocks, i. not just a simple bit to flip into a register. Once all the clocks have been shutdown the power dissipation is at most 300 mW (includes leakage current ˚C (case temperature). 5.4 Power Consumption ...
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... NXP Semiconductors Volume DC/AC I/O Characteristics The characteristics listed in the following tables apply to the worst case operating condition defined in digital ground). The following I/O characteristics includes the effect of process variation. PNX15XX_PNX952X_SER_N_4 Product data sheet PNX15xx/952x Series Section 5. on page 1-49. All voltages are referenced to VSS (0 V Rev. 4.0 — ...
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... NXP Semiconductors Volume 6.1 Input Clock Specification Table 22: Specification of HC-49U 27.00000 MHZ Crystal Frequency Temperature range Typical Load Capacitance ( Frequency accuracy (all included: temperature, aging, frequency Series resonance resistor Shunt capacitance ( Drive level External capacitance ( Figure X1 X2 Table 23: Specification of the Oscillator Mode ...
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... NXP Semiconductors Volume Table 24: SSTL_2 AC/DC Characteristics Symbol Parameter V DC Input High Voltage IH- Input Low Voltage IL- Input High Voltage IH- Input Low Voltage IL-AC R Series Output Resistance High/Low level output state SSTL T Slew rate, SLEW ( )/dt IH-AC IL-AC C Input pin capacitance IN [24-1] [24-2] ...
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... NXP Semiconductors Volume 6.3 BPX2T14MCP Type I/O Circuit Table 25: BPX2T14MCP Characteristics Symbol Parameter V Output High Voltage OH V Output Low Voltage Input High Voltage IHT V DC Input Low Voltage ILT V DC Input High Voltage Input Low Voltage IL Z Output AC Impedance O Pull Pull-up/down Resistor ...
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... NXP Semiconductors Volume 6.4 BPTS1CHP and BPTS1CP Type I/O Circuit Table 26: BPTS1CHP and BPTS1CP Characteristics Symbol Parameter V Output High Voltage OH V Output Low Voltage Input High Voltage IHT V DC Input Low Voltage ILT V DC Input High Voltage Input Low Voltage IL Z Output AC Impedance ...
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... NXP Semiconductors Volume 6.5 BPTS3CHP and BPTS3CP Type I/O Circuit Table 27: BPTS3CHP and BPTS3CP Characteristics Symbol Parameter V Output High Voltage OH V Output Low Voltage Input High Voltage IHT V DC Input Low Voltage ILT V DC Input High Voltage Input Low Voltage IL Z Output AC Impedance ...
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... NXP Semiconductors Volume 6.6 IPCHP and IPCP Type I/O Circuit Table 28: IPCHP and IPCP Characteristics Symbol Parameter V DC Input High Voltage IHT V DC Input Low Voltage ILT V DC Input High Voltage Input Low Voltage IL Pull Pull-up/down Resistor C Input pin capacitance IN 6.7 BPT3MCHDT5V and BPT3MCHT5V Type I/O Circuit ...
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... NXP Semiconductors Volume 6.8 IIC3M4SDAT5V and IIC3M4SCLT5V type I/O circuit Table 30: IIC3M4SDAT5V and IIC3M4SCLT5V Characteristics Symbol Parameter V Input High Voltage IH V Input Low Voltage IL V Input Schmitt trigger Hysteresis HYS V Output Low Voltage OL T Output Fall Time F C Input pin capacitance IN 6 ...
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... NXP Semiconductors Volume 7.1 Reset Figure 9: Table 32: Reset Timing Symbol Parameter T Reset active time after power and clock stable LOWP T Reset active after POR_IN_N is pulled high HOLD T Reset active time after power and clock stable LOWR [32-1] [32-2] [32-3] 7.2 DDR DRAM Interface PNX1500 supports DDR200, DDR266, DDR400{A,B,C} DDR devices as defi ...
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... NXP Semiconductors Volume Table 33: DDR DRAM Interface Timing Symbol Parameter T Maximum input skew supported iskew-dqs (when reading from DDR SDRAM) T Input setup time for MM_DQ is-dq (when reading from DDR SDRAM) T Input hold time for MM_DQ ih-dq (when reading from DDR SDRAM) ...
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... NXP Semiconductors Volume [34-7] Figure 10: PCI Output and Input Timing Measurement Conditions Figure 11: PCI T PNX15XX_PNX952X_SER_N_4 Product data sheet 6. For the purpose of Active/Float timing measurements, the Hi-Z or ‘off’ state is defined to be when the total current delivered through the component pin is less than or equal to the leakage current specification ...
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... NXP Semiconductors Volume 7.4 QVCP, LCD and FGPO Interfaces Table 35: QVCP, LCD and FGPO Timing With Internal Clock Generation Symbol Parameter F VDO_CLK1 frequency QVCP F VDO_CLK2 frequency FGPO T Clock to VDO_D[34:0] and VDO_AUX for PNX1502 CLK-DV Clock to VDO_D[34:0] and VDO_AUX for PNX1501 Clock to VDO_D[34:0] and VDO_AUX for PNX1500 ...
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... NXP Semiconductors Volume Figure 12: QVCP and FGPO I/O Timing [36-1] [36-2] [36-3] [36-4] [36-5] 7.5 VIP and FGPI Interfaces Table 37: VIP and FGPI Timing Symbol Parameter F VDI_CLK1 frequency VIP F VDI_CLK2 frequency FGPI T Input setup time SU-CLK T Input hold time H-CLK [37-1] ...
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... NXP Semiconductors Volume 7.6 10/100 LAN In MII Mode Table 38: 10/100 LAN MII Timing Symbol Parameter F LAN_CLK frequency LAN_CLK F LAN_TX_CLK and LAN_RX_CLK frequency CLK T Clock to LAN Outputs CLK-DV T Input setup time SU-CLK T Input hold time H-CLK [38-1] [38-2] [38-3] [38-4] Figure 14: LAN 10/100 I/O Timing in MII Mode 7 ...
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... NXP Semiconductors Volume [39-4] Figure 15: LAN 10/100 I/O Timing in RMII Mode 7.8 Audio Input Interface Table 40: Audio Input Timing Symbol Parameter F Audio Input oversampling frequency OSCLK F Audio Input frequency AI_CLK T Clock to AI_WS CLK-DV T Input setup time SU-CLK T Input hold time H-CLK ...
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... NXP Semiconductors Volume See timing measurement conditions Figure 16: Audio Input I/O Timing 7.9 Audio Output Interface Table 41: Audio Output Timing Symbol Parameter F Audio Output oversampling frequency OSCLK F Audio Output frequency AO_CLK T Clock to AO_WS and AO_SD[3:0] CLK-DV T Input setup time SU-CLK T Input hold time ...
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... NXP Semiconductors Volume See timing measurement conditions Figure 17: Audio Output I/O Timing 7.10 SPDIF I/O Interface Table 42: SPDIF I/O Timing Symbol Parameter T Data/Clock Output High Time HIGH T Data/Clock Output Low Time LOW T Data/Clock Input High Time IHIGH T Data/Clock Input Low Time ...
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... NXP Semiconductors Volume 7. I/O Interface 2 Table 43 I/O Timing Symbol Parameter f SCL clock frequency SCL T Bus free time BUF T Start condition set up time SU-STA T Start condition hold time H-STA T IIC_SCL LOW time LOW T IIC_SCL HIGH time HIGH T IIC_SCL and IIC_SDA fall time (Cb = 10-400 pF, from V ...
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... NXP Semiconductors Volume Figure 20: I 7.12 GPIO Interface Table 44: GPIO Timing Symbol Parameter F GPIO sampling/pattern generation CLOCK frequency CLOCK T GPIO[6:0] CLOCK to DATA valid for GPIO[15:0] pins CLK-DV1 T GPIO[6:0] CLOCK to DATA valid for GPIO[60:16] pins CLK-DV2 T Input setup time SU-CLK T Input hold time ...
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... NXP Semiconductors Volume See timing measurement conditions Figure 21: Audio Output I/O Timing 7.13 JTAG Interface Table 45: JTAG Timing Symbol Parameter F Boundary scan frequency BSCAN F JTAG frequency JTAG T Falling edge of the JTAG_TCK to JTAG_TDO CLK-DV T Input setup time SU-CLK T Input hold time H-CLK ...
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... NXP Semiconductors Volume Package Outline BGA456: plastic ball grid array package; 456 balls; body 1.75 mm ball A1 index area shape optional (4x) DIMENSIONS (mm are the original dimensions) A UNIT max. 0.6 1.85 0.7 27.2 mm 2.45 0.4 1.60 0.5 26.8 OUTLINE VERSION IEC SOT795-1 144E Figure 23: BGA456 Plastic Ball grid Array ...
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... NXP Semiconductors Volume BGA Ball Assignment Figure 24: BGA Bottom View Pin Assignment PNX15XX_PNX952X_SER_N_4 Product data sheet PNX15xx/952x Series Rev. 4.0 — 03 December 2007 Chapter 1: Integrated Circuit Data © NXP B.V. 2007. All rights reserved. 1-72 ...
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... NXP Semiconductors Volume Figure 25: BGA Top View Pin Assignment PNX15XX_PNX952X_SER_N_4 Product data sheet PNX15xx/952x Series Rev. 4.0 — 03 December 2007 Chapter 1: Integrated Circuit Data © NXP B.V. 2007. All rights reserved. 1-73 ...
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... NXP Semiconductors Volume 10. Board Design Guidelines The following sections discuss the fundamentals of board design for the PNX1500 system. The intent is to give general guidelines on the subject, not the complete in depth coverage. A minimum of four layers board is recommended. 10.1 Power Supplies Decoupling Power supply regulators require large smoothing capacitors to deliver the current until the regulator can follow the load conditions ...
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... NXP Semiconductors Volume Other devices like the DDR memory devices also require local decoupling capacitors. At least eight 0.1 F capacitors (one for each VDD or VDDQ) combined with one are recommended for each memory device. If board space allows an additional eight 0.01 per device is also recommended. ...
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... NXP Semiconductors Volume All the key components (the analog bypass capacitor and crystal capacitors) are on the PCB connected to the free-floating analog VSSA_1.2 net Figure 27: Digital VDD Power Supply to Analog VDDA/VSSA_1.2 Power Supply Filter Figure 28: Digital VDD Power Supply to Analog VDDA/VSSA_1.2 Power Supply Filter 10 ...
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... NXP Semiconductors Volume • Recommended Trace lengths for operating frequency DDR400 are shown in Table 46: DDR Recommended Trance Length Signal MM_CK, MM_CK# MM_AD[12:0], MM_BA[1:0] MM_RAS/CAS/WE/CKE MM_CS[1:0] MM_DQS[3:0] MM_DATA[31:0] MM_DQM[3:0] DDR devices that are DDR400{A,B,C} JEDEC compliant, revision JESD79C, have tDQSS defined as 0.72*tCK (min) and 1.25*tCK (max). Faster DDR devices have a more stringent requirement of 0 ...
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... NXP Semiconductors Volume and the bar of the ‘T’ (this applies when the signal has two or more loads). For single loaded tracks and bi-directional signals, the parallel termination resistor should be placed about 50% of the way to the DDR SDRAM device. For unidirectional signals and single loaded tracks, the termination should be placed after the pin of DDR SDRAM device ...
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... PNX1502E 12NC 9352 747 44557 300 MHz 200 MHz 1.3-V PNX1520E 12NC 9352 792 45557 266 MHz 183 MHz 1.3-V PNX1500E/G 12NC 9352 777 46557 240 MHz 183 MHz 1.2-V PNX1501E/G 12NC 9352 777 47557 266 MHz 200 MHz 1.2-V PNX1502E/G 12NC 9352 777 48557 300 MHz 200 MHz 1 ...
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... NXP Semiconductors Volume PNX15XX_PNX952X_SER_N_4 Product data sheet PNX15xx/952x Series Rev. 4.0 — 03 December 2007 Chapter 1: Integrated Circuit Data © NXP B.V. 2007. All rights reserved. 1-80 ...
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Chapter 2: Overview PNX15xx/952x Series Data Book – Volume Rev. 4.0 — 03 December 2007 1. Introduction The PNX15xx/952x Series Media Processor is a complete Audio/Video/Graphics system on a chip that contains a high-performance 32-bit VLIW processor, ...
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... NXP Semiconductors Volume Processing functions are those that modify an existing data structure and prepare that structure for display functions. Display functions take the processed data structures from memory and generate the appropriate output stream the case of the decode functions, display functions can be relatively simple, such multi-surface composited display ...
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... NXP Semiconductors Volume Table 1: Partitioning of Functions to Resources function image scaling video format conversions, including color space conversion histogram correction, black stretch, luminance sharpening (LTI, CDS, HDP), color features (green enhancement, skin tone correction, blue stretch, dynamic color transient improvement) display processing ...
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... NXP Semiconductors Volume • 2-layer compositing video output, with integrated scaling and video improvement processing, supporting W-XGA TFTs, 1280 x 768 60 Hz, HD video 1920 x 1080 Mpix/s. • Data Streaming and Message Passing ports with up to 400 MB/s bandwidth capability. • Variable Length Decoder assist engine. ...
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... NXP Semiconductors Volume PNX15xx/952x Series Functional Block Diagram Figure 1 Each component is further explained in this chapter and later more detailed with a dedicated chapter 200 MHz (i.e 400 MHz data rate), 16- or 32-bit wide DDR SDRAM 1.6 GB/s 656 data 656/data 32 data 2 8 ch. i ...
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... NXP Semiconductors Volume System Resources 3.1 System Reset The PNX15xx/952x Series includes a system reset module. This reset module provides a synchronous reset to internal PNX15xx/952x Series logic and a reset output pin for initialization of external system components. A system reset can be initiated in response to a board level reset input pin, a software configuration write result of a programmable watchdog timer time-out ...
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... NXP Semiconductors Volume The scripted boot, in combination with an appropriately programmed I allows the PNX15xx/952x Series to boot in many ways. A stand-alone PNX15xx/952x Series system is able to reliably update its own Flash boot image, whether the Flash is standard or nand Flash. In most systems this is done by extra Flash storage capacity that is used by the Flash update software to guarantee atomicity of a boot image update under power failure ...
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... NXP Semiconductors Volume – – – After wake-up from sleep mode, the TM3260 CPU can examine the tentative wake-up attempt, and if the wake-up is genuine, bring the system back to full operational mode. In addition, the clocks to individual unused modules can be turned off altogether and the idle() task of the operating system can be used to activate a voluntary powerdown mechanism in the CPU ...
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... NXP Semiconductors Volume System Memory 4.1 MMI - Main Memory Interface PNX15xx/952x Series has an unified memory system for the PNX15xx/952x Series CPU and all of its modules. This memory is also visible from any PCI master as PCI attached memory. The 32-bit DDR SDRAM interface can operate up to 200 MHz. This is equivalent to a 64-bit SDR SDRAM interface running at 200 MHz, resulting in theoretical available bandwidth ...
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... NXP Semiconductors Volume PNX15xx/952x Series provides 5 chip selects for the XIO bus. The TM3260 can execute or read from direct addressable Flash types. Execution from Flash is low performance, and only recommended for boot usage. After boot recommended that code files be transferred from Flash to DRAM where they can be executed more effi ...
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... NXP Semiconductors Volume The TM3260 is responsible for all media processing and real-time processing functions within the PNX15xx/952x Series. It runs a small real-time operating system, pSOS, which allows it to respond efficiently and predictably to real-time events. The TM3260 is capable of operating in little or big-endian mode. The mode is chosen shortly after CPU startup by setting the endian bit in the Program Control Status Word (PCSW) ...
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... NXP Semiconductors Volume MPEG Decoding The TM3260 processes the audio, video and the stream de-multiplexing via software. The Variable Length decoding as well as the authentication and the de-scrambling are supported by two coprocessors. 6.1 VLD The PNX15xx/952x Series VLD is an MPEG-1 and MPEG-2 parser that writes to memory a separate data structure for macro block header and coeffi ...
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... NXP Semiconductors Volume • Software (on the TM3260 CPU) can be written endian-mode independent, even when doing SIMD style vectorized computations Remark: The native formats of PNX15xx/952x Series include the most common indexed, packed RGB, packed YUV and planar YUV formats used by Microsoft DirectX and Apple Quicktime, with 100% bit layout compatibility in little and big-endian modes of operation, respectively ...
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... NXP Semiconductors Volume • Stores video data inside the video acquisition window in system memory in any of the native pixel formats indicated in rounding to convert the10-bit input to the selected format. • Provides an internal Test Pattern Generator with NTSC, PAL, and variable format support. • ...
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... NXP Semiconductors Volume • conversions from any input pixel format to any non-indexed pixel format, including conversions between 4:2:0, 4:2:2 and 4:4:4, indexed to true color conversion, color expansion / compression, de-planarization/planarization (to convert between planar and packed pixel formats, programmable color space conversion) • ...
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... NXP Semiconductors Volume – – – QVCP supports the semi-planar YUV formats for one layer. Both layers support only indexed, RGB and packed YUV formats. QVCP does not support planar video formats. See The mixer stage combines images from back to front, also allowing mixing fi ...
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... NXP Semiconductors Volume Motion vectors computed by TM3260 software can be sent to a video improvement post-processor over the PCI interface. The function of VDO_AUX is programmed using the QVCP capability to combine alpha or chroma-keying information during blending. For example, chroma keys in a graphics plane could be used to drive VDO_AUX. For another example, a threshold value for an alpha value of a graphics plane could be used to indicate whether a pixel is more than 80% video ...
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... NXP Semiconductors Volume Software decoded audio can be used for mixing with other audio for output along one of the audio outputs. The sample rate is determined by the S/PDIF source, and cannot be software controlled. 9. General Purpose Interfaces VIP and QVCP share a set of pins with two general purpose interface modules, FGPI and FGPO (respectively) ...
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... NXP Semiconductors Volume Table 6: Video/Data Input Operating Modes mode VIP function VDI_MODE[1:0] = 0x1 20-bit ITU 656 as for HD video with additional H&V synchronization signals VDI_MODE[1:0] = 0x2 8-bit ITU 656 or 8-bit raw data VDI_MODE[1:0] = 0x3 n/a In addition to controlling the operating mode of the VDI pins, VDI_MODE[7] bit controls the activation of a pre-processing module for the 8-bit data that is routed to the FGPI module. When VDI_MODE[7] = ‘ ...
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... NXP Semiconductors Volume The operating modes of the video/data output router are set by the VDO_MODE MMIO register. A subset of the operating modes is presented in behavior description of the output router is available in Section 7.5 module, while the FGPO module. Table 7: Video/Data Output Operating Modes mode QVCP function ...
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... NXP Semiconductors Volume • In combination with VDI_MODE[7] bit, see basic Video In module by storing in memory at specific locations the different lines and fields of the in-coming video data. Note that the YUV data is stored consecutively in memory and not stored in three different planes. 9.4 Fast General Purpose Output ...
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... NXP Semiconductors Volume Note that this capability is useful for low/medium speed software implemented protocols, as well as for observing switches, driving LEDs etc highly recommended to first use the powerful GPIO pins as protocol emulators, and not just for static switches/LEDs (for which a solution such as a PCF8574 I fi ...
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... NXP Semiconductors Volume • 50% of the pins will have a ‘low’ reset value • 50% have a ‘high’ reset value This allows use of GPIO for a variety of functions. 10.2 IR Remote Control Receiver and Blaster PNX15xx/952x Series uses the GPIO pin event sequence timestamping mechanism and software to interpret remote control commands ...
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... NXP Semiconductors Volume PNX15xx/952x Series as PCI master allows TM3260 to generate all single cycle PCI transaction types, including memory cycles, I/O cycles, configuration cycles and interrupt acknowledge cycles. As PCI target, PNX15xx/952x Series responds to memory transactions and configuration type cycles, but not to I/O cycles. ...
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... NXP Semiconductors Volume The table below summarizes extension capabilities of the bus interface unit. Table 9: PCI/XIO-16 Bus Interface Unit Capabilities External Device Device Type external PCI 32-bit MHz master PCI masters external PCI slave 32-bit MHz PCI targets external 8-bit slave 8- and 16-bit wide, de-muxed address / data devices on ‘ ...
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... NXP Semiconductors Volume Table 9: PCI/XIO-16 Bus Interface Unit Capabilities External Device Device Type external DRAM not supported external Motorola not supported style masters external 8/16-bit not supported XIO DMA devices 10.3.3 IDE Drive Interface The PNX15xx/952x Series contains an IDE controller that uses some of the PCI pins and a few sideband signals ...
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... NXP Semiconductors Volume PNX15xx/952x Series on-chip modules and co-processors observe the system global endian mode flag. The TM3260 endian mode can be set by the TM3260 program module itself, and should always be set identical to system endian mode. When selecting PCI peripherals for a dual-endian mode product, care must be taken to ensure that they can operate without ‘ ...
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... NXP Semiconductors Volume PNX15XX_PNX952X_SER_N_4 Product data sheet PNX15xx/952x Series Rev. 4.0 — 03 December 2007 Chapter 2: Overview © NXP B.V. 2007. All rights reserved. 2-108 ...
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Chapter 3: System On Chip Resources PNX15xx/952x Series Data Book – Volume Rev. 4.0 — 03 December 2007 1. Introduction This chapter presents information on the PNX15xx/952x Series System On-Chip (SOC) and its MMIO registers. Further details ...
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... NXP Semiconductors Volume Before going into the details of the three different views the following generic rules should be noted: • The three views must be consistent. For example not allowed to have a different DRAM aperture location for the TM3260 CPU and the PCI module. ...
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... NXP Semiconductors Volume Remark: Partial 32-bit load or stores from a PCI master to an MMIO register is not supported. Therefore byte of 16-bit half-word accesses are not supported. 2.2 The CPU View The TM3260 CPU supports three different apertures: • the MMIO aperture, used to access all the internal PNX15xx/952x Series registers ...
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... NXP Semiconductors Volume Remark: If the value 0x0000,0000 is stored into TM32_APERT1_HI, this value is understood as 0x1,0000,0000. 2.3 The DCS View Or The System View TM3260 0x1 0000 0000 inaccessible 2MB MMIO Aperture MMIO_BASE/base_14 inaccessible TM32_APERT1_HI APERT1 Aperture TM32_APERT1_LO inaccessible TM32_DRAM_HI non-cacheable TM32_DRAM_CLIMIT DRAM Aperture ...
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... NXP Semiconductors Volume the program phase where it is planned to be used). This creates random addresses that can target the APERT1 aperture. Therefore the load may generate a transaction on the PCI bus that may have some side effects. Furthermore the performance are deteriorated by a long CPU stall cycle that is dependent on the completion of PCI bus transaction (the CPU does not continue unless the read has completed) ...
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... NXP Semiconductors Volume 2.4.1 DCS DRAM Aperture Control MMIO Registers Table 1: SYSTEM Registers Acces Bit Symbol s DCS DRAM Aperture Control Registers Offset 0x06 3200 DCS_DRAM_LO 31:16 DCS_DRAM_LO R/W 15:0 Unused - Offset 0x06 3204 DCS_DRAM_HI 31:16 DCS_DRAM_HI R/W 15:0 Unused - Offset 0x06 3208 ...
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... NXP Semiconductors Volume Other than the PCI module, only the TM3260 CPU can emit requests to the PCI bus, i.e. none of the other PNX15xx/952x Series modules can do so. Only the TM3260 CPU and external PCI master can request MMIO reads or writes. The XIO aperture can only be accessed by the TM3260 CPU. ...
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... NXP Semiconductors Volume 3.3 System Module MMIO registers Table 2: SYSTEM REGISTERS Acces Bit Symbol s System Module Registers Offset 0x06 3FF4 GLB_REG_POWER_DOWN 31 POWER_DOWN R/W 30:0 Unused - Offset 0x06 3FFC GLB_REG_MOD _ID 31:16 MODULE_ID R 15:12 MAJOR_REV R 11:8 MINOR_REV R 7:0 APERTURE R 4. System Endian Mode ...
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... NXP Semiconductors Volume 4.1 System Endian Mode MMIO registers Table 3: SYSTEM REGISTERS Acces Bit Symbol s System Endian Mode Registers Offset 0x06 3014 SYS_ENDIANMODE 31:1 Unused - 0 BIG_ENDIAN R/W 5. System Semaphores PNX15xx/952x Series has 16 simple Multi-Processor (MP) semaphore-assist devices. They are built out of 32-bit registers, accessible through MMIO by either the local TM3260 CPU or by any other CPU located on the PCI bus through the aperture made available on the PCI module ...
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... NXP Semiconductors Volume • PCI configspace PERSONALITY entry. Each PNX15xx/952x Series receives a 16-bit PERSONALITY value from the EEPROM during boot. This PERSONALITY register is located at offset 0x40 in configuration space system, some of the bits of PERSONALITY can be individualized for each CPU involved, giving it a unique 2 4-bit ID, as needed given the maximum number of CPUs in the design. • ...
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... NXP Semiconductors Volume 5.5 Semaphore MMIO Registers Table 4: Semaphore MMIO Registers Acces Bits Symbol s Semaphore Registers Offset 0x06 3800 SEMAPHORE0 31:12 Unused - 11:0 SEMAPHORE0 R/W Offset 0x06 3804 SEMAPHORE1 31:0 SEMAPHORE1 R/W Offset 0x06 3808 SEMAPHORE2 31:0 SEMAPHORE2 R/W Offset 0x06 380C ...
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... NXP Semiconductors Volume Table 4: Semaphore MMIO Registers Acces Bits Symbol s 31:0 SEMAPHORE14 R/W Offset 0x06 383C SEMAPHORE15 31:0 SEMAPHORE15 R/W 6. System Related Information for TM3260 This section contains information on how the internal TM3260 resources like its interrupt lines or timers have been assigned or used in the PNX15xx/952x Series system. More specifi ...
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... NXP Semiconductors Volume Table 5: Interrupt Source Assignments SOURCE SOURCE NAME NUMBER TIMER3 7 SYSTIMER 8 VIP 9 QVCP SPDI 13 SPDO 14 ETHERNET 15 I2C 16 TMDBG 17 FGPI 18 FGPO 19 Reserved 20...21 MBS VLD 24 DVD-CSS 25 GPIO[10] 26 GPIO[11] 27 HOSTCOM 28 APPLICATION 29 DEBUGGER 30 RTOS 31 GPIO_INT0 32 GPIO_INT1 33 GPIO_INT2 34 GPIO_INT3 35 GPIO_INT4 36 PCI 37 PCI_GPPM 38 PCI_GPXIO ...
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... NXP Semiconductors Volume Table 5: Interrupt Source Assignments SOURCE SOURCE NAME NUMBER DCS 60 MMI 61 Reserved 62...63 6.2 Timers The TM3260 CPU contains four programmable timer/counters, all with the same function. The first three (TIMER1, TIMER2, TIMER3) are intended for general use. The fourth timer/counter (SYSTIMER) is reserved for use by the system software and should not be used by applications. Each timer/counter can be set to count one of the event types specifi ...
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... NXP Semiconductors Volume 6.3 System Parameters for TM3260 Few more control parameters are available to tune the use of TM3260 and PNX15xx/ 952x Series. The MMIO register layout and offsets are described in • The CPU apertures (DRAM and APERT1 described in modified by the TM3260 itself, if the TM32_APERT_MODIFIABLE bit is set to ‘1’. ...
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... NXP Semiconductors Volume 6.3.1 TM3260 Table 7: TM3260 System Parameters MMIO Registers Acces Bit Symbol s System Module Registers Offset 0x06 3700 TM32_CONTROL 31:4 Unused - 3 TM32_APERT_MODIFI R/W ABLE 2 TM32_LS_DBLLINE R/W 1 TM32_IFU_DBLLINE R/W 0 TM32_PWRDWN_REQ R/W Offset 0x06 3704 TM32_STATUS 31:1 Unused - 0 TM32_PWRDWN_ACK R 7. Video Input and Output Routers PNX15xx/952x Series provides two groups of high speed pins to stream data or video in and out. The input group of pins is prefi ...
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... NXP Semiconductors Volume Section 7.1 VDI_MODE and VDO_MODE MMIO registers. page 2-99 7.1 MMIO Registers for the Input/Output Video/Data Router In the following tables • The X associated with a bit value means ‘do not care’. • (clk_vip FF) means the data is registered by the clock assigned to VIP before presenting the signals to the VIP module. • ...
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... NXP Semiconductors Volume Table 8: Global Registers Acces Bit Symbol s Input and Output Control Registers Offset 0x06 3000 VDI_MODE 31:8 Unused - 7 VDI_MODE_7 R/W 6:5 Unused - PNX15XX_PNX952X_SER_N_4 Product data sheet Chapter 3: System On Chip Resources Value Description - To ensure software backward compatibility, writes to unused or reserved bits should be zero and reads must be ignored. ...
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... NXP Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 4:3 VDI_MODE[4:3] R/W 2 VDI_MODE[2] is unused - 1:0 VDI_MODE[1:0] R/W PNX15XX_PNX952X_SER_N_4 Product data sheet Chapter 3: System On Chip Resources Value Description 0 VDI-to-VIP mapping - XX000 10-bit ITU 656 10-bit raw data 0 VDI_V1-> (clk_vip FF)-> vip_dv_valid VDI_D[29:20] -> ...
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... NXP Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 4:3 VDI_MODE[4:3] R/W 2 VDI_MODE[2] is unused - 1:0 VDI_MODE[1:0] R/W 4:3 VDI_MODE[4:3] R/W 2 VDI_MODE[2] is unused - 1:0 VDI_MODE[1:0] R/W PNX15XX_PNX952X_SER_N_4 Product data sheet Chapter 3: System On Chip Resources Value Description 0 VDI-to-FGPI mapping - up to 20-bit data capture ...
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... NXP Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s Offset 0x06 3004 VDO_MODE 31:8 Unused - 7 VDO_MODE R/W PNX15XX_PNX952X_SER_N_4 Product data sheet Chapter 3: System On Chip Resources Value Description VDI-to-FGPI mapping (continued 24-bit data capture XX010: VDI_V2 -> (clk_fgpi FF) -> fgpi_d_valid VDI_D[23:0] -> (clk_fgpi FF) -> fgpi_data[23:0] VDI_D[32] -> ...
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... NXP Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 6 VDO_MODE R/W 5 VDO_MODE R/W 4:3 Unused - PNX15XX_PNX952X_SER_N_4 Product data sheet Chapter 3: System On Chip Resources Value Description 0 ‘0’: No action ‘1’: When VDO_MODE[2:0] = 100, i.e. digital 24-bit YUV or RGB video: ...
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... NXP Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 2:0 VDO_MODE R/W PNX15XX_PNX952X_SER_N_4 Product data sheet Chapter 3: System On Chip Resources Value Description 0 TFT/QVCP mapping to VDO interface 000*: TFT LCD controller with 24- or 18-bit digital RGB/YUV video TFT_DATA[23:0] -> VDO_D[28:5] TFT_VSYNC -> VDO_D[29] TFT_HSYNC -> ...
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... NXP Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s PNX15XX_PNX952X_SER_N_4 Product data sheet Chapter 3: System On Chip Resources Value Description 100*: Digital 24-bit YUV or RGB video QVCP_DATA[29:22,19:12,9:2] -> VDO_D[28:5] QVCP_VSYNC QVCP_HSYNC QVCP_AUX1 QVCP_CLK In 24-bit mode VDO_D[28:21] VDO_D[20:13] VDO_D[12:5] In 18-bit mode VDO_D[28:23] VDO_D[20:15] ...
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... NXP Semiconductors Volume Table 8: Global Registers …Continued Acces Bit Symbol s 2:0 VDO_MODE R/W [8-1] PNX15XX_PNX952X_SER_N_4 Product data sheet Value Description 0 FGPO mapping to VDO interface 000* and VDO_MODE[7] = ‘1’: FGPO_DATA[2:0] FGPO_DATA[3] FGPO_DATA[4] FGPO_DATA[5] FGPO_DATA[6] FGPO_DATA[7] FGPO_CLK 000* and VDO_MODE[7] = ‘0’: ...
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... NXP Semiconductors Volume Miscellaneous Several other system MMIO registers are described in the following paragraphs and detailed in the next • By default PCI_INTA_N is an input/output pin used in open drain mode for the PCI bus. When a host CPU wants to assert an interrupt to the TM3260 it asserts the PCI_INTA_N low ...
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... NXP Semiconductors Volume 8.1 Miscellaneous System MMIO registers Table 9: Miscellaneous System MMIO registers Acces Bit Symbol s System Registers Offset 0x06 3050 PCI_INTA 31:2 Unused - 1 PCI_INTA W 0 PCI_INTA_OE R/W Offset 0x06 3500 SCRATCH0 31:0 SCRATCH0 R/W Offset 0x06 3504 SCRATCH1 31:0 SCRATCH1 ...
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... NXP Semiconductors Volume Table 9: Miscellaneous System MMIO registers Acces Bit Symbol s Offset 0x06 3600 SPDI_MUX_SEL 31:4 Unused - 3:0 SPDI_MUX_SEL R/W Offset 0x06 360C SPARE_CTRL 31:8 Unused - 7:0 SPARE_CTRL R/W PNX15XX_PNX952X_SER_N_4 Product data sheet Chapter 3: System On Chip Resources …Continued Value Description - To ensure software backward compatibility, writes to unused or reserved bits should be zero and reads must be ignored ...
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... NXP Semiconductors Volume System Registers Map Summary Table 10: System Registers Map Summary Offset Name 0x06_3000 VDI _MODE 0x06_3004 VDO_MODE 0x06_3014 SYS_ENDIANESS 0x06_3050 PCI_INTA 0x06_3200 DCS_DRAM_LO 0x06_3204 DCS_DRAM_HI 0x06_3208 APERTURE_WE 0x06_3500 SCRATCH0 0x06_3504 SCRATCH1 0x06_3508 SCRATCH2 0x06_350C SCRATCH3 0x06_3510 SCRATCH4 0x06_3514 SCRATCH5 ...
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... NXP Semiconductors Volume Table 10: System Registers Map Summary Offset Name 0x06_383C SEMAPHORE15 0x06_3FF4 GLB_REG_PWR_DWN 0x06_3FFC GLB_REG_MOD _ID 10. Simplified Internal Bus Infrastructure Figure 3: Simplified Internal Bus Infrastructure More details on the DCS bus in PNX15XX_PNX952X_SER_N_4 Product data sheet …Continued Description 12-bit semaphore register. ...
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... NXP Semiconductors Volume 11. MMIO Memory MAP Each module has an address range in the MMIO aperture from which its registers can be accessed. This address range is defined by its starting address, a.k.a. its offset, and the aperture size defined in the MODULE_ID MMIO register. The following table gives the offset position for each module of the PNX15xx/952x Series system. Each module specifi ...
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... NXP Semiconductors Volume Table 11: MMIO Memory MAP address offset from MMIO_BASE Module Module (PCI base 14) Name ID 0x10,4000 GPIO 0xA065 0x10,6000 VIP 0x011A 0x10,9000 SPDIF OUT 0x0121 0x10,A000 SPDIF IN 0x0110 0x10,C000 MBS 0x0119 0x10,E000 QVCP 0xA052 0x11,0000 AO 0x0120 0x11,1000 AI 0x010D 0x1 0x1F,0000 ...
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Chapter 4: Reset PNX15xx/952x Series Data Book – Volume Rev. 4.0 — 03 December 2007 1. Introduction The Reset module initiates life for the PNX15xx/952x Series system since it generates all reset signals required for a correct ...
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... NXP Semiconductors Volume • peri_rst_n. This signal is used internally to reset all the PNX15xx/952x Series modules including the TM3260 CPU. This signal is asserted when one of the following conditions occurs: – – – – Remark: This signal does not reset the JTAG state machine, i.e. it does not assert jtag_rst_n. • ...
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... NXP Semiconductors Volume Figure 1 PNX15xx/952x Series system. Reset module Registers RST_CTL RST_CAUSE RESET_IN_N Watch Dog Timer POR_IN_N Interrupt Counter Bus Interface Figure 1: Reset Module Block Diagram 2.1 RESET_IN_N or POR_IN_N? POR_IN_N is meant to be used at power up of the system. By asserting this pin low ...
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... NXP Semiconductors Volume 2.2 The watchdog Timer The internal PNX15xx/952x Series watchdog timer has two operating modes. Both modes result in the assertion of the internal reset signals, peri_rst_n and sys_rst_out_n signals based upon a time-out condition. The modes are referenced as the non interrupt mode and the interrupt mode. ...
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... NXP Semiconductors Volume The following 1 clk_dtl_mmio 0 Watchdog_count watchdog_reset peri_rst_n sys_rst_out_n SYS_RST_OUT_N 1: The watchdog count register is programmed 2: The count is happening 3: The count reaches the programmed value and a watchdog reset is issued 4: Both the internal and the external resets are asserted Figure 2: Watchdog in Non Interrupt Mode 2.2.2 The Interrupt Mode In this mode, the watchdog timer generates fi ...
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... NXP Semiconductors Volume step 4 does not occur before the count reaches the WATCHDOG_COUNT value an interrupt is issued to the TM3260 CPU and the second internal counter (the interrupt counter) starts. The internal watchdog counter is reset and waits the interrupt to be cleared write with 0x1 to INTERRUPT_CLEAR stops the interrupt counter and restarts the watchdog counter ...
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... NXP Semiconductors Volume Remark: Upon any of the described ways to reset the PNX15xx/952x Series system the sys_rst_out_n remains asserted until a write with 0x1 occurs to the RST_CTL.REL_SYS_RST_OUT bit. 3. Timing Description 3.1 The Hardware Timing The assertion of POR_IN_N or RESET_IN_N signals causes the assertion of peri_rst_n, sys_rst_out_n and jtag_rst_n (only when POR_IN_N is asserted). See Figure the PNX15xx/952x Series modules receive the 27 MHz crystal oscillator input ...
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... NXP Semiconductors Volume 3.2 The Software Timing Whenever a watchdog timer time-out occurs or when a software reset is requested by writing to the RST_CTL.DO_SW_RST bit the PNX15xx/952x Series system is reset. Both are referred as software reset. As seen in the previous to hold the POR_IN_N or the RESET_IN_N signal for at least 100 s. Therefore the software reset mechanism implements an internal counter that allows to assert the peri_rst_n signal for 100 s ...
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... NXP Semiconductors Volume Register Definitions Table 1: RESET Module Acces Bit Symbol s Reset Module Offset 0x06,0000 RST_CTL 31:3 Unused W 2 DO_SW_RST W 1 REL_SYS_RST_OUT W 0 ASSERT_SYS_RST_O W UT Offset 0x06,0004 RST_CAUSE Remark: RST_CTL is set on every time an hardware or software reset occurs. 31:2 Unused 1:0 RST_CAUSE ...
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... NXP Semiconductors Volume Table 1: RESET Module …Continued Acces Bit Symbol s 0 WATCHDOG_INTERRU R/W PT_CLEAR Offset 0x06,0FEC INTERRUPT_SET 31:1 Unused R/W 0 WATCHDOG_INTERRU R/W PT_SET Offset 0x06,0FFC MODULE_ID 31:16 MODULE_ID R 15:12 MAJOR_REV R 11:8 MINOR_REV R 7:0 APERTURE R 5. References [1] “The TM3260 Architecture Databook”, Aug. 1st 2003, NXP. ...
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Chapter 5: The Clock Module PNX15xx/952x Series Data Book – Volume Rev. 4.0 — 03 December 2007 1. Introduction The Clock module is the heart of the PNX15xx/952x Series system. Its role is to provide and control ...
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... NXP Semiconductors Volume • programmable dividers, controlled by configuration registers • clock blocking circuitry to allow for safe, glitch-free switching of clocks. Clocks are typically switched when: – – – – PNX15XX_PNX952X_SER_N_4 Product data sheet PLLs or dividers are reprogrammed clocks are switched on/off for powerdown reasons ...
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... NXP Semiconductors Volume Figure 1 (DFT) have been added into the drawing and can be disregarded for functional behavior. The signals in functional operating mode. oscillator pad XTALI en xtal_clk low jitter PLL (external to CAB) XTALO PLL2 Custom Analog Block (CAB) 1.728 GHz pll1_7_fb sel_div_tst ...
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... NXP Semiconductors Volume Remark: Not all the clocks to the modules are generated in the Clock Module, there will be other clocks which will come into PNX15xx/952x Series from external sources. Some of these clocks will be fed through the Clock Module so that they may undergo the same controls required during reset, powerdown, DFT and DfD ...
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... NXP Semiconductors Volume Table 1: PNX15xx/952x Series Module and Bus Clocks Bus or Module Signal Name Description MBS clk_mbs MBS clock TMDBG clk_tstamp Timestamp clock GPIO 10/100 clk_lan Ethernet PHY Ethernet Clock MAC clk_lan_tx Ethernet Transmit Clock clk_lan_rx Ethernet Receiver Clock 2 IIC clk_iic ...
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... NXP Semiconductors Volume Table 1: PNX15xx/952x Series Module and Bus Clocks Bus or Module Signal Name Description QVCP clk_qvcp_out VDO_CLK1 External pixel clock clk_qvcp_pix internal pixel clock clk_qvcp_proc processing layer clock clk_lcd_tstamp LCD timestamp VIP clk_vip VDI_CLK1 External pixel clock VLD clk_vld MPEG-2 Variable ...
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... NXP Semiconductors Volume Table 1: PNX15xx/952x Series Module and Bus Clocks Bus or Module Signal Name Description GPIO clk_gpio_4q GPIO FIFO clock clk_gpio_5q GPIO FIFO clock clk_gpio_6q_12 GPIO FIFO clock/ external clock clk_gpio_13 external clock clk_gpio_14 external clock SPDIO clk_spdo SPDO module clock ...
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... NXP Semiconductors Volume 2.2.1 PLL Specification A PLL consists of a Voltage Controlled Oscillator (VCO) and a Post Divide (PD) circuit, as presented in Fpd Fin clk_in /M (xtal_clk) 5 extracted for DFT Figure 2: PLL Block Diagram The frequency from the VCO VCO F VCO F = out The bit width and 2 bits respectively. The N, M and P bits are programmable register bits in the Clock module control registers, PLL0_CTL and PLL1_CTL. PLL2_CTL does not allow to control the P parameter since it is fi ...
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... NXP Semiconductors Volume • Run the VCO as high as possible, therefore for low output frequencies chose high P values • Ensure Table 2: Current Adjustment Values Based on N 30-37 38-46 47-54 55-63 64-72 73-82 83-89 90-97 98-107 108-116 117-125 126-133 134-142 143-151 152-160 161-180 ...
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... NXP Semiconductors Volume PLL Characteristics Table 4: PLL Characteristics PLL Data Input clock frequency VCO input frequency VCO output frequency Output frequency Jitter (high frequency) Lock time Duty Cycle 2.2.2 The Clock Dividers The clock dividers allow to generate internally low jitter fixed clocks derived from the 1 ...
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... NXP Semiconductors Volume 2.2.3 The DDS Clocks The DDS clocks are recommended for clocks that need to track dynamically another frequency by very small steps. The following equations characterize the PNX15xx/ 952x Series DDS blocks: F DDS registers jitter step = 2.2.4 DDS and PLL Assignment Summary ...
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... NXP Semiconductors Volume 2.2.5 External Clocks Table 7 an external clock is any in-coming clock that feeds a PNX15xx/952x Series module or any internal PNX15xx/952x Series clock that can drive a PNX15xx/952x Series I/O pin. Table 7: External Clocks Signal Name Frequency xtal_clk 27 MHz clk_pci 33.23 MHz clk_pci_i ...
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... NXP Semiconductors Volume 2.3 Clock Control Logic All the generated PNX15xx/952x Series clocks follow the generic block diagram presented in CAB BLOCKING Logic re-program PLL parameters or 1.728 GHz PLL divider Figure 3: Block Diagram of the Clock Control Logic normal functional operating mode. The clock module allows several clock sources per clock signal. The different clock sources are selected with a multiplexer ...
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... NXP Semiconductors Volume The blocking will be released after a safe interval of 300 s. The 300 s is counted using the 27 MHz xtal_clk. blocking lasts for less than 10 xtal_clk cycles since it assumes the clocks are stable. xtal_clk clk_pll turn_off turn_off_ack clk_out Figure 4: Waveforms of the Blocking Logic ...
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... NXP Semiconductors Volume Table 8: Bypass Clock Sources Clocks from Clock Module clk_qvcp clk_qvcp_pix clk_qvcp_proc clk_lcd_tstamp clk_vip clk_vld ai_osclk ao_osclk clk_spdo clk_spdi clk_gpio_q4 clk_gpio_q5 clk_gpio_q6_12 clk_gpio_13 clk_gpio_14 clk_fgpo clk_fgpi 2.5 Power-up and Reset sequence On power-up, the Clock module outputs the default 27 MHz clocks to all the PNX15xx/952x Series modules ...
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... NXP Semiconductors Volume write with a 0 value stops the clock stretching circuit. clk_tm stretcher count 3 0 turn_off turn_off_ack clk_out Figure 5: Clock Stretcher 2.7 Clock Frequency Determination This feature allows the measuring of the internal PLL’s and DDS’s. This is used for basic test mode only ...
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... NXP Semiconductors Volume 2.8 Power Down All clocks generated in the clock module may be disabled by programming the relevant clock enable bit of each clock control register possible to gate module clocks in individual modules rather than in the Clock Module. The advantages of centralizing the clock gating are summarized in ...
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... NXP Semiconductors Volume The GPIO interrupt comes from the GPIO block and is the “OR” of all the FIFO and timestamp registers. This way a GPIO pin can be monitored and when an event occurs the interrupt to the processor awakes the system. Bit ‘0’ of the CLK_WAKEUP_CTL enables the GPIO interrupt ...
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... NXP Semiconductors Volume interrupt is generated whenever the signal 'clock present' changes status. Therefore an interrupt is generated if a clock changes from 'present' to 'non-present’ OR from 'non-present to 'present'. The interrupt registers are implemented using the standard peripheral interrupt module and can thus be enabled/cleared/set by software. ...
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... NXP Semiconductors Volume protecting an input clock from contention by having the pad set to an input (in the case of an input clock). In both cases a write to each control register is necessary to properly put the clock into an input or output configuration (otherwise the logic will remain in the quasi-input/output mode). ...
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... NXP Semiconductors Volume 2.12.1 TM3260, DDR and QVCP clocks Clock xtal_clk PLL2 is located outside CAB PLL2 N,M, current_adj parameters slice_tst_in CAB PLL1 DDS1 PLL1 slice_tst_in N,M,P 27 MHz parameters Duty cycle 75/25 CAB PLL0 DDS0 N,M,P slice_tst_in 27 MHz parameters DDSn control parameters ...
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... NXP Semiconductors Volume clk_144 clk_133 clk_108 clk_96 clk_86 clk_78 clk_58 clk_39 clk_33 clk_17 sel_qvcp_proc_clk_src Figure 8: QVCP_PROC Clock clk_qvcp_out Figure 9: QVCP_PIX Clock clk_qvcp_out generation is presented in clock used for clk_qvcp_out can be the inverted version of the clock present in the VDO_CLK1 pin. This allows the QVCP block to output data on the falling edge instead of the default positive edge ...
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... NXP Semiconductors Volume 2.12.2 Clock Dividers 1.728 GHz PLL CAB Figure 10: Clock Dividers PNX15XX_PNX952X_SER_N_4 Product data sheet PNX15xx/952x Series Clocks Block clk_192 / clk_173 / clk_157 / clk_144 / clk_133 / clk_123 / clk_115 / clk_108 / clk_102 / slice_tst_in Rev. 4.0 — 03 December 2007 Chapter 5: The Clock Module clk_192 ...
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... NXP Semiconductors Volume 2.12.3 Internal PNX15xx/952x Series Clock from Dividers clk_144 clk_123 clk_108 clk_96 clk_86 clk_78 clk_157 clk_72 clk_144 clk_54 clk_133 clk_123 clk_115 clk_108 clk_144 clk_102 clk_133 clk_54 clk_108 clk_96 clk_86 clk_78 clk_72 clk_66 sel_dtl_mmio_clk_src sel_vld_clk_src Figure 11: Internal PNX15xx/952x Series Clock from Dividers ...
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... NXP Semiconductors Volume clk_33 xtal_clk/16 clk_144 clk_72 UNDEF clk_108 clk_13_5 clk_48 Figure 12: Internal PNX15xx/952x Series Clock from Dividers: PCI, SPDI, LCD and I GPIO Figure 13: Internal PNX15xx/952x Series Clock from Dividers: LCD Timestamp PNX15XX_PNX952X_SER_N_4 Product data sheet GPIO xtal_clk BLOCKING BLOCKING BLOCKING ...
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... NXP Semiconductors Volume 2.12.4 GPIO Clocks Clock Module DDS8 tst_clk_a Clock Module DDS7 tst_clk_a Clock Module DDS6 tst_clk_a Clock Module DDS5 tst_clk_a Clock Module DDS2 tst_clk_a Figure 14: GPIO Clocks PNX15XX_PNX952X_SER_N_4 Product data sheet xtal_clk tst_clk_gpio_q4 BLOCKING GPIO sel_clk_gpio_q4_ctl xtal_clk tst_clk_gpio_q5 BLOCKING ...
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... NXP Semiconductors Volume 2.12.5 External Clocks xtal_clk DDS7 GPIO sel_clk_vip clk_vip Figure 15: VDI_CLK1 Block Diagram sel_clk_fgpi_src DDS3 DDS8 GPIO sel_clk_fgpi clk_fgpi Figure 16: VDI_CLK2 Block Diagram PNX15XX_PNX952X_SER_N_4 Product data sheet Clock Module vip_output_enable_n slice_tst_out tst_clk_vip BLOCKING sel_clk_vip/reset BLOCKING xtal_clk Clock Module fgpi_output_enable_n ...
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... NXP Semiconductors Volume xtal_clk PLL1 GPIO sel_clk_qvcp clk_lcd clk_qvcp_out qvcp_output_enable_n qvcp_output_select invert_clk_qvcp Figure 17: VDO_CLK1 Block Diagram xtal_clk PLL1 UNDEF DDS2 GPIO sel_clk_fgpo_src sel_clk_fgpo clk_fgpo Figure 18: VDO_CLK2 Block Diagram PNX15XX_PNX952X_SER_N_4 Product data sheet Clock Module qvcp_output_enable_n tst_clk_qvcp slice_tst_out clk_qvcp BLOCKING note: lcd clock path ...
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... NXP Semiconductors Volume Audio Output Module tps_ao_sck_oen tps_ao_sckout clk_ao_sck_o slice_tst_out DDS3 Figure 19: AO Clocks Audio Input Module tps_ai_sck_oen tps_ai_sckout clk_ai_sck_o slice_tst_out DDS4 Figure 20: AI Clocks PNX15XX_PNX952X_SER_N_4 Product data sheet Clock Module BLOCKING AO_SCK_CTL slice_tst_clk xtal_clk PLL1 BLOCKING GPIO AO_OSCLK_CTL tst_clk_a Clock Module ...
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... NXP Semiconductors Volume UNDEF PLL1 DDS4 DDS7 sel_clk_lan_clk_src Figure 21: PHY LAN Clock Block Diagram CLK_LAN_R/TX Figure 22: Receive and Transmit LAN Clocks PNX15XX_PNX952X_SER_N_4 Product data sheet tst_clk_lan xtal_clk BLOCKING GPIO sel_clk_lan slice_tst_clk xtal_clk sel_clk_lan slice_tst_clk Rev. 4.0 — 03 December 2007 PNX15xx/952x Series ...
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... NXP Semiconductors Volume 2.12.6 SPDO DDS5 Figure 23: SPDO Clock 3. Registers Definition 3.1 Registers Summary Table 10: Registers Summar Offset Name 0x04,7000 PLL0_CTL 0x04,7004 PLL1_CTL 0x04,7008 PLL2_CTL 0x04,700C PLL1_7_CTL 0x04,7010 DDS0_CTL 0x04,7014 DDS1_CTL 0x04,718 DDS2_CTL 0x04,701C DDS3_CTL 0x04,7020 DDS4_CTL 0x04,7024 DDS5_CTL 0x04,7028 DDS6_CTL ...
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... NXP Semiconductors Volume Table 10: Registers Summar Offset Name 0x04,7124 CLK_IIC_CTL 0x04,7128 CLK_DVDD_CTL 0x04,712C CLK_MMIO_CTL 0x04,7130- RESERVED 0x04,71FC 0x04,7200 CLK_QVCP_OUT_CTL 0x04,7204 CLK_QVCP_PIX_CTL 0x04,7208 CLK_QVCP_PROC_CTL 0x04,720C CLK_LCD_TSTAMP_CTL 0x04,7210 CLK_VIP_CTL 0x04,7214 CLK_VLD_CTL 0x04,7218- RESERVED 0x04,72FC 0x04,7300 AI_OSCLK_CTL 0x04,7304 AI_SCK_CTL 0x04,7308 AO_OSCLK_CTL 0x04,730c AO_SCK_CTL 0x04,7310 ...
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... NXP Semiconductors Volume Table 10: Registers Summar Offset Name 0x04,7FEC INTERRUPT_SET 0x04,7FF0- RESERVED 0x04,7FF8 0x04,7FFC MODULE_ID PNX15XX_PNX952X_SER_N_4 Product data sheet PNX15xx/952x Series Description Set Clock Detection interrupts RESERVED Module Identification and revision information Rev. 4.0 — 03 December 2007 Chapter 5: The Clock Module © ...
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... NXP Semiconductors Volume 3.2 Registers Description Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s PLL Registers Offset 0x04,7000 PLL0_CTL Reset values set for expected frequencies for faster boot-up, shorter boot code. 31:30 Reserved R/W 29 Turn Off Acknowledge R 28 PLL Lock R 27:24 pll0_adj ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s Offset 0x04,7008 PLL2_CTL Reset values set for expected frequencies for faster boot-up, shorter boot code. 31:30 Reserved R/W 29 Turn Off Acknowledge R 28 PLL Lock R 27:24 pll2_adj R/W 23:21 Reserved R/W 20:12 ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s Offset 0x04,701C DDS3_CTL 31 Enable R/W 30:0 dds3_ctl[30:0] R/W Offset 0x04,7020 DD4_CTL 31 Enable R/W 30:0 dds4_ctl[30:0] R/W Offset 0x04,7024 DDS5_CTL 31 Enable R/W 30:0 dds5_ctl[30:0] R/W Offset 0x04,7028 DDS6_CTL 31 Enable R/W 30:0 dds6_ctl[30:0] ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 1 pd_108 R/W 0 pd_102 R/W Offset 0x04,7038-0x04,70FCReserved Module Clocks Offset 0x04,7100 CLK_TM_CTL 31:6 Reserved R/W 5 turn_off_ack R 4 tm_stretch_n R/W 3 sel_pwrdwn_clk_mmio W 2:1 sel_clk_tm R/W 0 en_clk_tm R/W Offset 0x04,7104 CLK_MEM_CTL 31:4 Reserved R/W ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 3 turn_off_ack R 2:1 sel_clk_mem R/W 0 en_clk_mem R/W Offset 0x04,7108 CLK_2DDE_CTL 31:7 Reserved R/W 6 turn_off_ack R 5:3 sel_clk_2dde_src R/W 2:1 sel_clk_2dde R/W 0 en_clk_2dde R/W Offset 0x04,710C CLK_PCI_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_pci ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 6 turn_off_ack R 5:3 sel_clk_mbs_src R/W 2:1 sel_clk_mbs R/W 0 en_clk_mbs R/W Offset 0x04,7114 CLK_TSTAMP_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_tstamp R/W 0 en_clk_tstamp R/W Offset 0x04,7118 CLK_LAN_CTL 31:6 Reserved R/W 5 turn_off_ack R 4:3 sel_lan_clk_src ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 2:1 sel_clk_lan R/W 0 en_clk_lan R/W Offset 0x04,711C CLK_LAN_RX_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_lan_rx R/W 0 en_clk_lan_rx R/W Offset 0x04,7120 CLK_LAN_TX_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_lan_tx R/W 0 en_clk_lan_tx R/W Offset 0x04,7124 ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 6 turn_off_ack R 5:3 sel_clk_dvdd_src R/W 2:1 sel_clk_dvdd R/W 0 en_clk_dvdd R/W Offset 0x04,712C CLK_DTL_MMIO_CTL 31:7 Reserved R/W 6 turn_off_ack R 5:3 sel_clk_dtl_mmio_src R/W 2:1 sel_clk_dtl_mmio R/W 0 en_dtl_mmio R/W Offset 0x04,7200 CLK_QVCP_OUT_CTL 31:7 Reserved R/W ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 5 Invert_qvcp_clock R/W 4 qvcp_output_select R/W 3 qvcp_output_enable_n R/W 2:1 sel_clk_qvcp R/W 0 en_clk_qvcp R/W Offset 0x04,7204 CLK_QVCP_PIX_CTL 31:7 Reserved R/W 6 turn_off_ack R 5:3 div_clk_qvcp_pix R/W 2:1 sel_clk_qvcp_pix R/W PNX15XX_PNX952X_SER_N_4 Product data sheet …Continued Value ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 0 en_clk_qvcp_pix R/W Offset 0x04,7208 CLK_QVCP_PROC_CTL 31:8 Reserved R/W 7 turn_off_ack R 6:3 sel_clk_qvcp_proc_src R/W 2:1 sel_clk_dtl_mmio R/W 0 en_clk_proc R/W Offset 0x04,720C CLK_LCD_TIMESTAMP_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_lcd_timestamp R/W 0 en_clk_lcd_timestamp R/W Offset 0x04,7210 ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 3 vip_output_enable_n R/W 2:1 sel_clk_vip R/W 0 en_clk_vip R/W Offset 0x04,7214 CLK_VLD_CTL 31:7 Reserved R/W 6 turn_off_ack R 5:3 sel_clk_vld_src R/W 2:1 sel_clk_vld R/W 0 en_clk_vld R/W Offset 0x04,7300 AI_OSCLK_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 31:3 Reserved R/W 2 turn_off_ack R 1 sel_clk_ai_sck R/W 0 en_clk_ai_sck R/W Offset 0x04,7308 CLK_AO_OSCLK 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_ao_osclk R/W 0 en_ao_osclk R/W Offset 0x04,730C CLK_AO_SCK_CTL 31:3 Reserved R/W 2 turn_off_ack R 1 sel_clk_ao_sck R/W ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 4 turn_off_ack R 3 sel_spdi_clk_src R/W 2:1 sel_spdi_clk R/W 0 en_clk_spdi R/W Offset 0x04,7318-0x04,73FCReserved General Purpose Offset 0x04,7400 CLK_GPIO_Q4_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_gpio_q4_ctl R/W 0 en_clk_gpio_q4_ctl R/W Offset 0x04,7404 CLK_GPIO_Q5_CTL 31:4 Reserved ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 2:1 sel_clk_gpio_q6_12_ctl R/W 0 en_clk_gpio_q6_12_ctl R/W Offset 0x04,740C CLK_GPIO_13_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_gpio_13_ctl R/W 0 en_clk_gpio_13_ctl R/W Offset 0x04,7410 CLK_GPIO_14_CTL 31:4 Reserved R/W 3 turn_off_ack R 2:1 sel_clk_gpio_14_ctl R/W 0 en_clk_gpio_14_ctl R/W Offset 0x04,7414 ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 5 fgpo_output_enable_n R/W 4:3 sel_clk_fgpo_src R/W 2:1 sel_clk_fgpo R/W 0 en_clk_fgpo R/W Offset 0x04,7418 CLK_FGPI_CTL 31:6 Reserved R/W 5 turn_off_ack R 4 fgpi_output_enable_n R/W 3 sel_clk_fgpi_src R/W 2:1 sel_clk_fgpi R/W 0 en_clk_fgpi R/W Offset 0x04,741C-0x04,74FCReserved Debug Registers ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 31:0 count_stretcher_bits R/W Offset 0x04,7504 CLK_WAKEUP_CTL 31:2 count_wakeup_bits R/W 1 external_wakeup_enabl R gpio_interrupt_enable R/W Offset 0x04,7508 CLK_FREQ_CTL 31:5 freq_ctr_bits 4 freq_ctr_done 3:0 en_ctr_enable Offset 0x04,750C CLK_COUNT_RESULTS 31:0 freq_ctr_results Offset 0x04,7510 ALIGNER_ADJUST (RESERVED DO NOT MODIFY) ...
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... NXP Semiconductors Volume Table 11: CLOCK MODULE REGISTERS Acces Bit Symbol s 9:8 Aligner_adjust_area2 7:6 Aligner_adjust_area1 5:4 Aligner_adjust_l_area0 3:2 Aligner_adjust_e_area0 1:0 Aligner_adjust Offset 0x04,7514-FDC RESERVED Interrupt Registers Offset 0x04,7FE0 INTERRUPT STATUS 31 VDO_CLK2_present R 30 VDI_CLK2_present R 29 ao_sckin_present R 28 ai_sckin_present R 27 VDI_CLK1_present R 26:5 Reserved R/W ...