SL811HS Cypress Semiconductor Corp, SL811HS Datasheet - Page 10

• Manufacturer Part Number: SL811HS
• Description: IC USB HOST/SLAVE CTRLR 28PLCC
• Manufacturer: Cypress Semiconductor Corp

Specifications of SL811HS

• Applications: USB Host/Slave Controller
• Controller Series: USB-Hosts
• Ram Size: 256 x 8
• Interface: USB
• Number Of I /o: 8
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: 0°C ~ 65°C
• Mounting Type: Surface Mount
• Package / Case: 28-PLCC
• For Use With: CY3662 - KIT DEVELOPMENT EZ-811HS
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Core Processor: -
• Program Memory Type: -
• Other names: 428-1463

Document 38-08008 Rev. *D
Interrupt Status Register, Address [Address = 0Dh]. The Interrupt Status register is a READ/WRITE register providing
interrupt status. Interrupts are cleared by writing to this register. To clear a specific interrupt, the register is written with corre-
sponding bit set to ’1’.
Table 14. Interrupt Status Register [Address 0Dh]
Current Data Set Register/Hardware Revision/SOF Counter LOW [Address = 0Eh]. This register has two modes. Read
from this register indicates the current SL811HS silicon revision.
Table 15. Hardware Revision when Read [Address 0Eh]
Writing to this register sets up auto generation of SOF to all connected peripherals. This counter is based on the 12 MHz clock
and is not dependent on the crystal frequency. To set up a 1 ms timer interval, the software must set up both SOF counter registers
to the proper values.
Bit Position
Bit 7
Bit 7
Bit Position
D+
7
6
5
4
3
2
1
0
7-4
3-2
1-0
Detect/Resume
D+
Device Detect/Resume Device Detect/Resume Interrupt.
Insert/Remove
SOF timer
Reserved
Reserved
USB-B
USB-A
Bit Name
Device
Bit 6
Bit 6
Hardware Revision
Hardware Revision
Reserved
Reserved
Bit Name
Insert/Remove
Bit 5
Bit 5
Value of the Data+ pin.
Bit 7 provides continuous USB Data+ line status. Once it is determined that a device
is inserted (as described below) with bits 5 and 6, bit 7 is used to detect if the inserted
device is low speed (0) or full speed (1).
Bit 6 is shared between Device Detection status and Resume Detection interrupt.
When bit-6 of register 05h is set to one, this bit is the Resume detection Interrupt bit.
Otherwise, this bit is used to indicate the presence of a device, ’1’ = device ‘Not present’
and ’0’ = device ‘Present.’ In this mode, check this bit along with bit 5 to determine
whether a device has been inserted or removed.
Device Insert/Remove Detection.
Bit 5 is provided to support USB cable insertion/removal for the SL811HS in host mode.
This bit is set when a transition from SE0 to IDLE (device inserted) or from IDLE to
SE0 (device removed) occurs on the bus.
‘1’ = Interrupt on SOF Timer.
‘0’
‘0’
USB-B Done Interrupt. (See description in Interrupt Enable Register [address 06h].)
USB-A Done Interrupt. (See description in Interrupt Enable Register [address 06h].)
Function
SL811HS rev1.2 Read = 1H; SL811HS rev1.5 Read = 2.
Read is zero.
Reserved for slave.
Function
SOF timer
Bit 4
Bit 4
Reserved
Bit 3
Bit 3
Reserved
Bit 2
Bit 2
Reserved
USB-B
Bit 1
Bit 1
SL811HS
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USB-A
Bit 0
Bit 0