CY7C64113C-PVXC Cypress Semiconductor Corp, CY7C64113C-PVXC Datasheet - Page 14

• Manufacturer Part Number: CY7C64113C-PVXC
• Description: IC MCU 8K FULL SPEED USB 48-SSOP
• Manufacturer: Cypress Semiconductor Corp
• Series: M8™r

Specifications of CY7C64113C-PVXC

• Applications: USB Microcontroller
• Core Processor: M8C
• Program Memory Type: OTP (8 kB)
• Controller Series: CY7C641xx
• Ram Size: 256 x 8
• Interface: I²C, USB, HAPI
• Number Of I /o: 36
• Voltage - Supply: 4 V ~ 5.25 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-SSOP
• For Use With: 428-1339 - KIT LOW SPEED PERSONALITY BOARD
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

resonator does not allow the microcontroller to meet the timing
specifications of full speed USB and therefore a ceramic
resonator is not recommended with these parts.
An external 6-MHz clock can be applied to the XTALIN pin if the
XTALOUT pin is left open. Grounding the XTALOUT pin when
driving XTALIN with an oscillator does not work because the
internal clock is effectively shorted to ground.
Reset
The CY7C64x13C supports two resets: Power-On Reset (POR)
and a Watchdog Reset (WDR). Each of these resets causes:
■
■
■
■
The occurrence of a reset is recorded in the Processor Status
and Control Register, as described in
Control Register on page
occurrence of POR and WDR, respectively. Firmware can
interrogate these bits to determine the cause of a reset.
Program execution starts at ROM address 0x0000 after a reset.
Although this looks like interrupt vector 0, there is an important
difference. Reset processing does NOT push the program
counter, carry flag, and zero flag onto program stack. The
firmware reset handler should configure the hardware before the
“main” loop of code. Attempting to execute a RET or RETI in the
firmware reset handler causes unpredictable execution results.
Power-On Reset (POR)
When V
signal
The USB transmitter is disabled by a Watchdog Reset because
the USB Device Address Register is cleared. Otherwise, the
USB Controller would respond to all address 0 transactions.
It is possible for the WDR bit of the Processor Status and Control
Register (0xFF) to be set following a POR event. The WDR bit
should be ignored If the firmware interrogates the Processor
Status and Control Register for a Set condition on the WDR bit
and if the POR (bit 3 of register 0xFF) bit is set.
Document Number: 38-08001 Rev. *D
all registers to be restored to their default states,
the USB Device Address to be set to 0,
all interrupts to be disabled,
the PSP and Data Stack Pointer (DSP) to be set to memory
address 0x00.
CC
is
is first applied to the chip, the Power-On Reset (POR)
asserted
and
25. Bits 4 and 6 are used to record the
Last write to
Watchdog Timer
Register
the
CY7C64x13C
Processor Status and
t
Figure 2. Watchdog Reset (WDR)
WATCH
No write to WDT
register, so WDR
goes HIGH
enters
a
2 ms
“semi-suspend” state. During the semi-suspend state, which is
different from the suspend state defined in the USB specification,
the oscillator and all other blocks of the part are functional,
except for the CPU. This semi-suspend time ensures that both a
valid V
stabilize before full operation begins. When the V
above approximately 2.5 V, and the oscillator is stable, the POR
is deasserted and the on-chip timer starts counting. The first
1 ms of suspend time is not interruptible, and the semi-suspend
state continues for an additional 95 ms unless the count is
bypassed by a USB Bus Reset on the upstream port. The 95 ms
provides time for V
before the chip executes code.
If a USB Bus Reset occurs on the upstream port during the
95-ms semi-suspend time, the semi-suspend state is aborted
and program execution begins immediately from address
0x0000. In this case, the Bus Reset interrupt is pending but not
serviced until firmware sets the USB Bus Reset Interrupt Enable
bit (bit 0 of register 0x20) and enables interrupts with the EI
command.
The POR signal is asserted whenever V
approximately 2.5 V, and remains asserted until V
this level again. Behavior is the same as described above.
Watchdog Reset (WDR)
The Watchdog Timer Reset (WDR) occurs when the internal
Watchdog timer rolls over. Writing any value to the write-only
Watchdog Restart Register at address 0x26 clears the timer. The
timer rolls over and WDR occurs if it is not cleared within t
(8 ms minimum) of the last clear. Bit 6 of the Processor Status
and Control Register is set to record this event (the register
contents are set to 010X0001 by the WDR). A Watchdog Timer
Reset lasts for 2 ms, after which the microcontroller begins
execution at ROM address 0x0000.
Suspend Mode
The CY7C64x13C can be placed into a low-power state by
setting the Suspend bit of the Processor Status and Control
register. All logic blocks in the device are turned off except the
GPIO interrupt logic and the USB receiver. The clock oscillator
and PLL, as well as the free-running and Watchdog timers, are
shut down. Only the occurrence of an enabled GPIO interrupt or
non-idle bus activity at a USB upstream or downstream port
CC
Execution begins at
Reset Vector 0x0000
level is reached and that the internal PLL has time to
CC
to stabilize at a valid operating voltage
CY7C64013C
CY7C64113C
CC
CC
Page 14 of 53
drops below
CC
rises above
has risen
WATCH
[+] Feedback